Computex 2019 - AMD teased new Ryzens 3. gen (launch 7.7.2019)

[zanzabar]

As for the IO die, yes, the one for EPYC is diffrent, its so big it can have cache on it.But it would simply not fit on am4 package. From what ive seen, for Am4 there is one IO die, the same for 1 and 2 chiplet cpus.

It sounded like epyc and ryzen 2 would the same but double the parts (4 cpu die, 2 IO die, with them being the same or very similar.) That is why I want those white papers. It might turn out that the cores have the same cache as before, but the IO chip doubles it for each cpu die connected.

If it was like that then I dont see how you get the 64/128 lane PCI-e.