Quote Originally Posted by zanzabar View Post
They are adding support for 4000mhz ram without overclocking the memory controller. That should really help with the latency.

They also may have a different cache structure it looks like it has cache on the IO controller as well, and that there are different io chip configurations for 1 or 2 cpu die configurations. They should have much more info closer to launch.
I didnt see any talk about that, could you link to the rumours of 2 different IO dies on ryzen platform ? (epyc will have its own and that we know).
As for the IO size, if you subtract cores from zeppelin die, you are left with pretty much exactly the die size that IO has, so no space really for L4 cache.I jope im wrong tho