AMD "Steamroller/Excavator" -info, speculations and experience

[demonkevy666]

@demonkevy666

Learn the difference between socket and platform.

LGA 2011 is a PLATFORM FOR HIGH END DESKTOP

LGA 1150 IS A PLATFORM FOR MID RANGE DESKTOP

Socket changes can be part of a platform change for features.
Chipsets changes small features like how many raids it can use or how high the Bus speed can go.

Now if WE can back topic THIS thread is ABOUT STEAMROLLER, Not platforms

[EniGmA1987]

I saw this info posted on another forum and wanted to see what people here think about it. This is from the AMD supplied gcc "machine descriptor" file:

;; AMD bdver3 Scheduling
;;
;; The bdver3 contains three pipelined FP units and two integer units.
;; Fetching and decoding logic is different from previous fam15 processors.
;; Fetching is done every two cycles rather than every cycle and
;; two decode units are available. The decode units therefore decode
;; four instructions in two cycles.
;;
;; Three DirectPath instructions decoders and only one VectorPath decoder
;; is available. They can decode three DirectPath instructions or one
;; VectorPath instruction per cycle.
;;
;; The load/store queue unit is not attached to the schedulers but
;; communicates with all the execution units separately instead.
;;
;; bdver3 belong to fam15 processors. We use the same insn attribute
;; that was used for bdver3 decoding scheme.

Zambezi and Vishera are supposed to do 4 instructions per clock cycle I thought, it looks like this is saying Steamroller design will do 2 instructions per clock cycle? I thought adding the second decoder so each core has its own again was supposed to increase IPC, not decrease it. I dont seem to understand it, which is why I hope the smart people from this forum can help explain what this actually means.

[Darakian]

I saw this info posted on another forum and wanted to see what people here think about it. This is from the AMD supplied gcc "machine descriptor" file:




Zambezi and Vishera are supposed to do 4 instructions per clock cycle I thought, it looks like this is saying Steamroller design will do 2 instructions per clock cycle? I thought adding the second decoder so each core has its own again was supposed to increase IPC, not decrease it. I dont seem to understand it, which is why I hope the smart people from this forum can help explain what this actually means.

Any chance you can link to the full file? It sounds like the fetching is being delayed in order to hide latency on the decode units (give them a cycle to flush stuff out).

[haylui]

I saw this info posted on another forum and wanted to see what people here think about it. This is from the AMD supplied gcc "machine descriptor" file:




Zambezi and Vishera are supposed to do 4 instructions per clock cycle I thought, it looks like this is saying Steamroller design will do 2 instructions per clock cycle? I thought adding the second decoder so each core has its own again was supposed to increase IPC, not decrease it. I dont seem to understand it, which is why I hope the smart people from this forum can help explain what this actually means.

someone replied in Overclock.net forum

http://www.overclock.net/t/1404574/steamroller/300

[EniGmA1987]

Any chance you can link to the full file? It sounds like the fetching is being delayed in order to hide latency on the decode units (give them a cycle to flush stuff out).

http://gcc.gnu.org/ml/gcc-patches/20...1079/bdver3.md


I am wondering if maybe AMD feels that the majority of work for the CPU will be "double instructions" which take two cycles to decode, and thus the scheduler is only active every other cycle?

;; Double instructions take two cycles to decode.

Im just trying to wrap my head around why AMD would move from running fetching and decoding every cycle, to only fetching every other. To me it just seems like it would be a step back in performance. And if you are now fetching only half as often, what point is there in doubling the decode units in the first place?

[The Stilt]

KaveriPI (AGESA):

- Support for KV-B0 stepping.
- "Spectre" & "Spooky" HUMA GOP VBIOS
- DCT0, DCT1, DCT2, DCT3 config array

Loving the GPU codenames

[Khenglish]

KaveriPI (AGESA):

- Support for KV-B0 stepping.
- "Spectre" & "Spooky" HUMA GOP VBIOS
- DCT0, DCT1, DCT2, DCT3 config array

Loving the GPU codenames

The main problem I see with quad channel memory is that people then need 4 memory sticks. While this is not a big deal for desktops, only high end laptops with dGPUs have 4 slots.

Unless maybe AMD is planning their own special 128bit memory? I don't think they have the clout to pull that off though. The industry adopting 128bit memory would be great though. Huge performance gains for IGPs and even a bit for CPUs. Cheaper boards can just support single channel to keep motherboard costs as they are today, but only 1 memory stick would be needed to match current bandwidth. Higher end motherboards can support dual channel for 256bit total memory bandwidth.

[The Stilt]

The main problem I see with quad channel memory is that people then need 4 memory sticks. While this is not a big deal for desktops, only high end laptops with dGPUs have 4 slots.

Unless maybe AMD is planning their own special 128bit memory? I don't think they have the clout to pull that off though. The industry adopting 128bit memory would be great though. Huge performance gains for IGPs and even a bit for CPUs. Cheaper boards can just support single channel to keep motherboard costs as they are today, but only 1 memory stick would be needed to match current bandwidth. Higher end motherboards can support dual channel for 256bit total memory bandwidth.

Entry level setups rarely feature a high-end APU.
Only the high-end (Spectre) GPU is fast enough to make the quad channel mandatory.
The downcored / clocked versions will be just fine with DDR-2133 dual channel DRAM, just like the current high-end GPUs are.

4x DDR-1333 modules are generally cheaper than 2x DDR-2133 modules, while the bandwidth is nearly 25% greater.

[Khenglish]

Entry level setups rarely feature a high-end APU.
Only the high-end (Spectre) GPU is fast enough to make the quad channel mandatory.
The downcored / clocked versions will be just fine with DDR-2133 dual channel DRAM, just like the current high-end GPUs are.

4x DDR-1333 modules are generally cheaper than 2x DDR-2133 modules, while the bandwidth is nearly 25% greater.

Hmm I just see few laptops supporting quad channel. Remember APU laptops, even the top ones, are budget laptops. There's limited space to add 2 more memory slots and the necessary signal routing to them on smaller laptops. Even on laptops that do have the room it still adds to costs. They already sell them with cheap 1600 ram so I don't see how they can use 4 slower sticks to cut costs significantly. The only way would be to use all 2GB sticks, but that will still cost more than 2 4GB, or 1 4GB with 1 2GB, which is what most cheap laptops come standard with.

It should be a phenomenal performance increase though for the laptops makers who do put the 4 slots in with 4 modules, but unfortunately I see most laptops getting gimped in some way.

[FlanK3r]

KaveriPI ?? What means DCT2, DCT3 ...?

[Olivon]

DCT3 means quad channel I guess (ABCD)
DCT0 + DCT1 is dual channel (AB) if I'm not mistaking.

[informal]

Yup, that's it Olivon.
Thanks for sharing the info Stilt .

[AbortRetryFail?]

KaveriPI (AGESA):

- Support for KV-B0 stepping.
- "Spectre" & "Spooky" HUMA GOP VBIOS
- DCT0, DCT1, DCT2, DCT3 config array

Loving the GPU codenames

The AC-130s might be seeing some 'close-in' action in the next few weeks ... if boots hit the ground.

I like *PI* ... not sure what the significance of it is, if any, either.

[EniGmA1987]

Where could the rest of us find the source with that AGESA code so that we can view it?

[The Stilt]

Where could the rest of us find the source with that AGESA code so that we can view it?

You can take a look at it at Coreboot.org (until KabiniPI), however the code for Kaveri is under NDA and therefore currently unavailable.

[zir_blazer]

You can take a look at it at Coreboot.org (until KabiniPI), however the code for Kaveri is under NDA and therefore currently unavailable.

Interesing that you mention Coreboot. I considered it as a potential alternative to get AMD-Vi working on Motherboards of brands that don't care about implementing that feature correctly. However, according to this list, they only had one FM2 Motherboard and pretty much nothing else modern or interesing. I would love to see that project grow, but for as long as they distribute only source code, the amount of people that is capable of actually porting the source to a given Motherboard is rather small. I suppose that if they sticked to some popular mainstream Motheboards and released BIN files ready to flash like manufacturers do, more people would try it.

[The Stilt]

Doesn't matter the code for each models are still there (AGESA) to be viewed.

[Mechanical Man]

http://techreport.com/news/25279/des...ri-not-delayed

So, not delayed. In time still. Feb '14 in stores, ships late this year.. will see, will see.

[Khenglish]

http://techreport.com/news/25279/des...ri-not-delayed

So, not delayed. In time still. Feb '14 in stores, ships late this year.. will see, will see.

Well "on time" if you consider Feb '14 on time, which most people don't. AMD delays everything CPU side though so in a way it is on time for them.

[tbone8ty]

fm2+ mobos with 8 memorys slots lol

[Lightman]

fm2+ mobos with 8 memorys slots lol

Sounds fun, but I still think we will get 4 DIMM slots as standard, but each DIMM driven by independent DCT.
They should clock nicely though!

[FlanK3r]

i think the same, maybe for future in enxt 2-3 years...If you see DRAM support, you cna see 3000 OC DRAM in memory dividier at FM2+

[imamage]

So far I saw Gigabyte show off G1.Sniper for FM2+ platform
http://www.gigabyte.com/products/pro...px?pid=4683#ov
I hope they do release some A88X uATX (mATX) board

[The Stilt]

So far I saw Gigabyte show off G1.Sniper for FM2+ platform
http://www.gigabyte.com/products/pro...px?pid=4683#ov
I hope they do release some A88X uATX (mATX) board

F2A88X-UP4 is still the enthusiast targeted model.
Unlike the other Sniper-series boards (Intel), the G1.Sniper A88X is nothing but a mainstream motherboard equipped with higher grade audio. The Sniper uses 4+2 phase analog VRM while the F2A88X-UP4 features a 6+2 phase digital VRM.

Personally I would rather see a 4+4 phase VRM for the high-end FM2r2 motherboards, as the relative power density of the iGPU on Kaveri is higher than ever before.

[Fottemberg]

F2A88X-UP4 is still the enthusiast targeted model.
Unlike the other Sniper-series boards (Intel), the G1.Sniper A88X is nothing but a mainstream motherboard equipped with higher grade audio. The Sniper uses 4+2 phase analog VRM while the F2A88X-UP4 features a 6+2 phase digital VRM.

Personally I would rather see a 4+4 phase VRM for the high-end FM2r2 motherboards, as the relative power density of the iGPU on Kaveri is higher than ever before.

Gigabyte writes that F2A88X-UP4 is a 8+2: http://www.gigabyte.com/products/pro...px?pid=4709#ov