AMD "Steamroller/Excavator" -info, speculations and experience

[Darakian]

I saw this info posted on another forum and wanted to see what people here think about it. This is from the AMD supplied gcc "machine descriptor" file:




Zambezi and Vishera are supposed to do 4 instructions per clock cycle I thought, it looks like this is saying Steamroller design will do 2 instructions per clock cycle? I thought adding the second decoder so each core has its own again was supposed to increase IPC, not decrease it. I dont seem to understand it, which is why I hope the smart people from this forum can help explain what this actually means.

Any chance you can link to the full file? It sounds like the fetching is being delayed in order to hide latency on the decode units (give them a cycle to flush stuff out).