SSD Write Endurance 25nm Vs 34nm

[sergiu]

Just an idea that hit me... couldn't a MLC SSD be used as a SLC with half capacity after those rated P/E cycles have been depleted? Underneath, both SLC and MLC cells are similar, so binary values 00 and 01 could be easily mapped to 0 while 10 and 11 could be mapped as 1. This would allow higher margins for ADC circuit to interpret the values and could lead to less errors due to data retention, as most probably the charge is not lost completely, but just entered in an undefined zone. So, does anybody know if this would be technically possible? or there are some less known hardware limitations?

Later edit:
Found something interesting on subject: http://www.usenix.org/event/usenix09...rs/lee/lee.pdf