@ Boris: I've never suggested 95W @ 5 GHz but the 32nm process is borked. I think AMD has a much bigger clue what they did then anyone on enthusiast forums. There have been designs before with long pipelines and high frequencies that worked, IBM Power6 reached over 5 GHz on a 65nm-process. IPC is irrelevant it's the relation of IPC and clock frequencies that really matters. Advantage is in theory a lower amount of transistors/die area thus needing less transistors to power but you need higher frequencies. Obviously AMD dropped the ball here, but the concept none the less works if properly executed.

I am not expecting miracles from Piledriver, only that the path AMD choose will start making sense compared to K10. And the manufacturing process they are using are severely borked so there are increases in frequency and power efficiency to be had here.