AMD "Piledriver" refresh of Zambezi - info, speculations, test, fans

[-Boris-]

-Boris-
can you show me some proof, because some parts are so wrong, mainly 2x performance per mm2, I really want to know how you got that and the same or higher frequencies is just a wet dream o yours, its enough if you look at Llano with disabled IGP, that cpu can't break the 4Ghz barrier while BD is attacking 5Ghz and is made on the same 32nm process.

p.S. I agree on higher IPC and perf/w is worse only on 4module but still on par with Thuban, the 3module and 2 module are better than anything else from AMD. Example Llano 2.9Ghz has the same power consumption as FX4100 but FX is a few % better.
Even FX6100 has a higher consumption by just 4% but performs better by 15% the rest of AMD cpu has higher power draw.

I said on 32nm! And I know, we don't exactly know how Phenom II would perform on 32nm, but it wouldn't be worse than 45nm. How do I know? GloFos 32nm isn't that bad since it already manages two really large dies. I think it's fairly safe that Thuban would reach a bit higher frequencies at early 32nm at almost half the size of BD, and with BDs or Llanos better IMC and Llanos IPC improvements it would already there equal a few hundred MHz extra performance. There you have at least 10% higher performance than Thuban at almost half the size of BD, and that with plenty of headroom to grow in!
And as I said many times before, you can't use Llano as an example of the performance of GloFos 32nm. It's a 1.45 billion trannie monster, with almost no "easy" trannies and die space like caches, it's all complex logic. And it has tradeoffs we don't know anything about. A GPU design originally designed for TSMCs low power and low frequency processes for larger dies with more shaders wouldn't work very good at a high power and high frequency process, like the ones you make CPUs on. Just as a CPUs would have a hard time reaching high frequencies if made on a process tuned for wide low frequency chips like a GPU. And another reason for Llanos bad overclocking abilities is that it has no frequency limiters and is locked, thus raising the bus raises a lot of frequencies that shouldn’t be touched. No one says Intels 32nm is bad just because SBs doesn’t overclock good at all when locked.

Bulldozer: 315 mm2

Thuban: 346 mm2


Just to add that GF's 45 nm process is capable for higher performance than the current 32 nm one.

Seriously? Quote mining much? You forgot the last part of the sentence "Phenom II has higher performance per watt, twice(!) the performance per mm² (taking processes in to account)." I honestly thought our discussion would be above your quote mining tactics. And your chart just proves my point. Phenom II DOES have higher performance per watt! And if shrunk with 32nm it would be almost half as big, but even cooler and capable of even higher performance! There you have twice the performance per mm². And no, no one has presented any proof that 32nm is very bad at all, of course it might not be the best process right now, but if it's capable right from the start to make two gargantuan chips it can't be too bad, and it would most likely perform much better on smaller chips, like Thuban.

I am not going to say Bulldozer is great cause it isn't. Facts are it was designed with power efficiency in mind and something has gone terribly wrong with the architecture, and we won't know for sure if these problems can be resolved until we see Piledriver to be honest.

And clocks aren't "near the roof" - far from it. AMD have for the past two quarterly results said explicitly they aren't happy with 32nm performance at GlobalFoundries and have overall been very open about it. Bulldozer was designed with high frequencies which shows as it retails at 3,6 GHz base. Llano was aimed at >3,0 GHz and reached only 2,9 GHz at launch and lets not speak of the mobile models. There are no problems releasing a CPU with clocks above 4,0 GHz and good power efficiency as long as it was designed for it (IPC usually gets cut then) which was a design compromise AMD did.

The manufacturing process isn't good at all today, and AMD decided to launch a brand new architecture on an unproven manufacturing process (never done by AMD nor Intel ever before?). I will wait for Piledriver before I pass any judgment on the architecture as a whole. I don't expect it to rock anyones world, but it will most likely be better than K10 and Phenom II.

First, AMDs current projections on Piledriver doesn't show it being that much better. It just can't magically get twice the performance per mm² it needs to have to be competitive in the long run. And no process scales very good with frequencies above 3-4GHz. That's the reason BD fails, they made huge tradeoffs for frequencies that have a very high price. The differences needed in an architecture or a process to earn an extra GHz at these levels are huge! In the past we could see 50-100% frequency increase with each process, sometimes even more, today, a new process don't give you that. You can still make larger and more complex chips, but not much have happened with frequencies since the 3GHz barrier was broken many years ago. So if an action that usually gave you a lot of frequency headroom in the past no longer does that, how much do you have to do to earn 1-2GHz that AMD needs right now? When closing in to 4GHz intels speed demon P4 couldn't go higher, and designs that were made for lower frequencies kept rising in speed until high IPC A64 and Core 2 were capable of almost the same frequencies. Higher IPC has the same costs it always had, but higher frequencies today require larger tradeoffs than ever before. That's why relatively huge tradeoffs in BD haven't given more than a few hundred MHz, which Thuban on 32nm might have reached just as well.

So, you simply can't make BD at 5GHz and 95W, and that’s where it needs to be to at least be competitive with SB mid-range, not taking BDs enormous die size into account. It would be easier to make a 32nm Thuban with IPC improvements at 95W, and it would have room to grow in. So yes, BD is pretty close to the roof, the roof might be just a bit over 4GHz in base clock, and it needs to be much much higher.

And no, no design can eradicate transistor level leakage. In the old days before leakage was a big problem you could make designs for higher frequencies, but not today, both low-IPC and high-IPC designs suffer from the same leakage at the same high frequencies. The larger the die the larger the problem as it usually means voltage increase. In a leakage free world then half as long steps in the pipe could mean twice the frequency, but if you run into massive leakage problems that grow exponentially with frequency and voltage then both designs suffer from this at the same frequencies. So to tune down IPC to get more frequency is to ask for more heat generated at the same performance today. This is just the same story all over again as when Prescott had it's problems, people blamed the process, even then Dothan shined on the same process, the difference was that the speed demon Prescott already was pushing the roof.


Simply put, to be just a bit competetive with SB then BD would need to be 5GHz at 95w with a much smaller die. No process can fix that! And how will it go with IB which seems to gain an even larger performance per watt advantage over PD. The situation might be even worse between PD and IB!