AMD "Piledriver" refresh of Zambezi - info, speculations, test, fans

[BeepBeep2]

I would imagine feeding > 2 Billion transistors instead of ~900 Million would cause a bit of current jump.
2 Billion is just ridiculous, and to think that resources have to be shared with that many transistors, has me scratching my head.

You would think that shrinking the exact same die would at least use same or less power draw on 32nm than 45nm nomatter how bad it is as well.
No matter what math you do and facts you show, a lot of people in this section will disagree and show you benchmarks that utilize all 8 clusters and how they beat Thuban by 10% @ 5 Ghz vs Thuban at 4.2. Then you come back with a single thread perf slide and they all look at you with their hands over their ears and go "NA NA NA NA NA", ignoring it. Then they say, well, it must have been GloFo's fault. BD is a good chip, look, it does better than my Thuban in benchmark A and F! ...you look and tell them, "what about benchmarks B, C, D, E?" ...they look at you and say "It's because those programs don't take advantage of Bulldozer's new instruction sets! That's why...new software will take advantage of them." (Despite the fact that intel dominates the market and programs are 90% of the time optimized for intel platforms) Then you look at them tell them that AMD should have shrunk X6, including Llano's updated cores for 5% IPC increase over current Thuban, and optimized cache, maybe worked on the northbridge so it was closer to this BD northbridge (further increasing IPC) and increased Mhz. They start running out of answers and say stupid like "IPC isn't everything" and post up AIDA memory bandwidth results at 2300 ram clock or whatever. Then they argue about how BD equals or beats SB in multithreaded apps albeit at a 30% higher power draw. Thuban could have done that on 45nm, clocked high enough. Here we go blaming the manufacturing process again.

AMD could have squeezed another 8 to 10% IPC out of the current architecture had they increased L2 to 1MB, integrated Llanos revised core, added a few MB of L3 (Thuban IPC was lower than Deneb due to less L3 cache) and revised the IMC to bring the type of memory bandwidth the new CPU brings. Instead, we have this fail called Bulldozer.

I could go on with my rant, but others will still look down upon me for looking at facts.

I'll buy BD, only because I was dumb enough to buy a 990FX board before BD came from out of NDA.