Quote Originally Posted by Cecil View Post
Most of the loss in MT is from the loss in ST. The 4 module design should roughly equal 7 cores (assuming the MT app scales 100%). With each core of each module not being as fast as a Deneb/Thuban core, there is a shared performance drop on all the modules.

What they basicaly did is revert back to a quad core and give it a form of hardware level HT that scales better, but lost ST performance by doing so.
The problem is, they would have been much more competitive with Sandy Bridge if they had shrunk X6 (I'm not sure why guys keep saying "add two cores!"), added 4-6MB between L2 and L3 caches, and sped stock speeds up to 3.6-4.0 single thread. I'm fairly certain that is doable within a 95-125w TDP on 32nm, and they should have been able to figure out some way to gain clockspeed...intel has had no problems with it, and AMD did it well from transition to 65nm to 45.

X6's that would OC on water 4.6-4.7 Ghz on 32nm +3% IPC boost from extra cache or adopted Llano's STARS core + L3, would have gained ~5-10% IPC over current gen and would have been a lot better than this.