AMD Zambezi news, info, fans !

[freeloader]

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

[BeepBeep2]

no one knows the the exact scaling because its hidden behind NDA.
and if they did stick with PII architecture it would be more than 3% because llano does quite nicely for not having and L3. it would also pack in more true cores. by omitting the extra space used for the second thread of the module, the core itself got bigger with BD, so IPC should be higher or they found ways to waste more space. (btw your option 2 makes no sense, why reduce IPC since they can easily pack in 8 old cores in BDs size, and why would that drop the clocks by 400mhz)

i honestly dont believe in just 6pts for BD at 3.6ghz, and if that is the case its probably on the very low end of the spectrum for how it handles otherwise it would be a step backwards.

Maybe I'm the stupid one here...
Llano's IPC difference vs Propus is neglegible. It's worth about 100 Mhz...or roughly 3%. Sure, up to 5% in some apps...too bad we are 30% behind Sandy with "STARS". As far as AMD's efficiency falling with more cores? Yeah. Thuban is a slower CPU in single thread than Deneb (partially due to less cache)...but look it up.

I leave you with a long string of quotes from chew in this thread that were posted in reaction to BD's leaked performance, ending with a response to freeloader:
By the way, VR-Zone Cinebench leak has shown ~5x scaling over all cores from single thread (not one whole module-core like the patent design states)
Regardless of what is behind NDA and what is not, between what we have for current leak and what chew* has said, I expect scaling from 5.0 to 5.5x on retail chips.

I see it as a 4 core part that can execute up to 8 threads, An engineer at AMD while I was there tended to agree with me, but what does he know.........

We obviously have members here that know more about BD than AMD.

Thuban had the same tdp but lost effeciency core per core to deneb if you guys all forgot about that, so you shrink it maybe increase ipc which will increase tdp somewhat.......you can do one of two things, scale clocks and be right back at same tdp or add two more cores, sacrifice scaling, that's really not an option.

An 8 core thuban would have been damn close to gulfy in multithreaded however.

Said it before and will say it again.

TDP.........

If you shrunk thuban to 32nm you could do 1 of 2 things, add 2 cores or increase clocks......not both, there's no room to grow.

Apparently according to AMD's roadmap however with bulldozer there is room to grow and stay within TDP limitations......

*insert flank3r post about how X8 would be a multithreading beast*

...I've been claiming far before bulldozer talk how well "STARS" does multithreaded, if multithread was AMD's focus they should have stayed with it in my opinion. On 45nm, it was very competetive with Lynnfield and Bloomfield multithreaded.

Maybe but you missed the other part i mentioned.........Where do you go from there.

You have no room to grow so your back to square 1 and need a new architecture to build on.

Wow someone with common sense...........

Like i said before I discussed this face to face with engineers at AMD, BD is a native 4 core 8 thread part.

and then the lynch mob got mad..........

I'm just gonna put this little bit out there.

There is more than 1 way to skin a cat.

Why is there still an on going discussion of core's modules.........

I don't give a rats ass what Marketing calls the chip.

AMD's patent draws a clear picture. They say a picture says a 1000 words right? AMD's own picture for there own patent.

Note core 100 not module 100 aka core 0, and then inside core 0 is 2 clusters A and B.

Case closed.

Attachment 120124

Only reason I have tried to point this out many times so far is due to peoples expectations. Those expecting 100% native 8 core multithreaded performance have unrealistic expectations. Hopefully this gives them a better idea so they can have more realistic expectations.

Engineers > Marketing when it comes to what's really what.

It's microcode injected into a bios.

For every cpu generation and or revision the microcode can be tuned/optimized and even without a silicon revision.

From there board partners can play around and "tweak" it even more via bios.

There are many bios options that can effect the outcome of benches.

HPET is 1 for example, it stops the cpu from throttling back in mulithreaded apps.

Running pi on a cluster, versus a core ( 2 threads ) versus being able to disable a single cluster in a core ( which 99% boards/bios's do not have implemented so resources are not shared ) can all influence the results in single threaded.

Knowing all this tells you one thing for sure, you can make it look worse or make it look better all depending on your knowledge of the chip and or your intentions.

As far as PI it's an antiquated bench and has not been AMD's strong point for quite some time.

Granted some results shown tend to lead to the fact that 1m times are bad but looking at the bigger picture we also know that in many cases you can validate 1000mhz higher in many cases with BD, which would point to the fact that you can run 1m at alot faster speeds than current AMD tech.

Things that make you go hmm like what kind of times will we see at 8 gig or even comparing BD to deneb/thuban when same cooling is used.

*insert more arguements about how ty BD is and its not 4 cores blah blah, cinebench sucks it sucks blah blah*

Actually it's not. For whatever reason amd chose to market it as cores.

In reality however BD is more akin to 4 cores / 8 threads as they share resources.

I have said this since the beginning.

There are however other reasons for calling them cores.

Example you can disable HT with intel.

AMD's design to my knowledge however does not allow for disabling a core in a module, I could be wrong however.

These ARE cores in Zambezi. It is from hardware and software perspective a true 8 core processor.Each module can retire 8 macroops per cycle(4 per core). Each core has a dedicated FMAC (And an additional FMAC if opportunity arises). The fact that cores share certain parts is because this is a smart thing to do from engineering POV. You save space and improve performance and perf./watt.
In the end,why would consumers even care? If it performs like an 8 core processor for all intents and purposes,why wouldn't people refer to it as to an 8 core processor(even if they don't personally think it is one)?

...some example talk, because PR said it was true and the website said it was true, and AMD has a habit of either
A. Not talking to public
B. Talking to public (not us enthusiasts directly...like Simon) in horrible ways, misleading info, cheesy presentations, how Denebs with disabled cores are a "True Dual Core Design?"

There is no debate about how many it has. AMD has designated 8 so 8 it is........

Regardless of all those specs, docs and whitepapers you can dredge up I am telling people how it works.

If they wish to not accept that fact.....well thats their problem.

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

I'd give that CPU a launch speed of 3 Ghz. New processes, GF lagging behind and seemingly sucking at yields looks like trouble with new process.
As far as 12MB of cache...triple channel memory controller, two more cores...about 45-50% more die space (rough estimate, larger DDR3 controller + reorder cores for 3+3+2 and AMD's horrible cache density equalling 15% of Thubans die (6MB)) on a 40% shrink so you are looking at 5% larger than thuban around 350-375 mm^2? Leaves no room at all to grow, even if they could pull that off.

[informal]

BeepBeep, I admit that I have no clue about what was your intention with the last post. Summary of quotes plus some vague estimate how much die area would X8 K10 have? Who cares about 32nm X8 K10? It's not going to happen so why discuss it? And as for Bulldozer ,there are so many unknowns that it's not even funny. We have no real/official benchmark on final platform, no official launch date, no shipping date for Zambezi and no official price. We do have some bits and pieces here and there,some painting good some bad picture. That's all.

[EniGmA1987]

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

Thats not an upgrade, thats an entirely new processor architecture

[BeepBeep2]

BeepBeep, I admit that I have no clue about what was your intention with the last post. Summary of quotes plus some vague estimate how much die area would X8 K10 have? Who cares about 32nm X8 K10? It's not going to happen so why discuss it? And as for Bulldozer ,there are so many unknowns that it's not even funny. We have no real/official benchmark on final platform, no official launch date, no shipping date for Zambezi and no official price. We do have some bits and pieces here and there,some painting good some bad picture. That's all.

It really should have been three or four posts...and I seem to add on to my thoughts so a lot of information does get jumbled up.

Ignore my jumbled response to manicdan + freeloader on "stars" arch to 8 cores on 32nm and the effects it would have on performance + die space. (in freeloaders case, 8 core with 12MB L3 + tri channel memory) would be a larger die on 32nm than thuban is on 45nm.

As far as Bulldozer:
Yes you are right, no "real" official benchmarks.

But there are two peices of information available:
chew*'s words about how the architecture is more like a 4 core with HT + leaked unofficial benchmarks that show multi-threading performance in several cases lower than Thuban, making some people assume that IPC is lower than Deneb. People are looking at these results and dividing by 7 to 8 for "theoretical leaked single thread performance" and talking about how IPC is lower. Maybe it is(!)

...chew* states that running a program as simple as pi on two cores "one module" brings better SINGLE thread performance, goes back to what I predicted a month ago as soon as he said the architecture works more like a 4 core with HT the first time.

Several weeks ago, my prediction was this:
Higher IPC in 4 threads or less
Lower IPC in more than four threads, but better scaling than HyperThreading.

Hopefully this post is a little easier to understand

EDIT:
Cleaned up the first post a bit if you'd like to take another stab at it.

[Naturecannon]

BeepBeep, I admit that I have no clue about what was your intention with the last post.

I think his point is: Read between the lines of the post's from one who has had vast experience with AMD chips and hands on with BD. Read the clues!! Has come to the same conclusion as me..... BD wont be the monster everyone is hoping for.

I also believe the events this summer, rumors and delays point to the same thing.

Disclaimer: ^ My personal opinion, hope I am wrong and the 5 years of BD planning nets a real winner for the enthusiast .

[BeepBeep2]

I think his point is: Read between the lines of the post's from one who has had vast experience with AMD chips and hands on with BD. Read the clues!! Has come to the same conclusion as me..... BD wont be the monster everyone is hoping for.

I also believe the events this summer, rumors and delays point to the same thing.

Disclaimer: ^ My personal opinion, hope I am wrong and the 5 years of BD planning nets a real winner for the enthusiast .

People in the AMD crowd seem to be way too hung up on multi-threaded performance and the fact that AMD calls this an 8 core CPU(even though they've been crying about single thread but pretending like more cores makes up for it, hence "why didn't they make X8 32nm").

Because leaked benchmarks show the 8 core CPU performing near 2500K level multithreaded, people are disappointed. However, chew* has stated multiple times the CPU internally is a 4 core with 8 threads. People have simply given him hell for making such statements. The funny thing here to me though, is that he has Bulldozer and they do not.

The goal here in my opinion was not to add more cores, but to get single thread performance up. If they can find a way to make CMT work well (1 thread per module) and that does in fact speed up single thread performance, then I see absolutely nothing wrong with this architecture. If you guys haven't noticed, Sandy cores are huge...Llano cores are not. Bulldozer modules are huge...Llano cores are not. 1 Sandy Core = 2 threads...1 BD module = 2 threads.

[dess]

CMT = AMD HT in physical form that can not be turned off, trumping Intel's HT.

Don't call it HT, in relation to AMD, please. HyperThreading is a brandname of Intel for its implementations of SMT.
So, CMT is a kind of Multi Threading. A quite different one to SMT. Otherways both are "physical".

I agree that it's a 4-core + CMT, from engineering POV. Altough, if it performs comparably to a true 8-core of earlier uarch's, then it can be valid to call it a 8-core.

[EniGmA1987]

...chew* states that running a program as simple as pi on two cores "one module" brings better SINGLE thread performance, goes back to what I predicted a month ago as soon as he said the architecture works more like a 4 core with HT the first time.

But we have known the processor would act like a 4 core + advanced hyper threading for what, 2 years now? Maybe 3? Everyone got caught up in the whole 8 core thing but we have known for a LONG time now that this architecture that uses cluster multi threading was just a more advanced and better form of HT. It was talked about extensively years ago by AMD. Slides were shown explaining the 4 types of multi-threading in a core and why AMD hadn't done the same thing as Intel and what AMD would do and was trying to implement in Bulldozer for its multi-threaded cores.

[rog]

Just 5,95 pts in Cinebench: http://www.donanimhaber.com/islemci/...onuclari_5.htm

[marten_larsson]

To calculate single thread performance one should look at JF's posts. One thread = 100% two threads =180%, this is probably top scaling so probably lower most often, maybe 40-60%. If BD IPC is less than 11% higher than Thuban it will not increase IPC per two threads (111% of Thuban + 88% of thuban) best case scenario. In non optimal scenarios it would need from 25-50% higher IPC than Thuban to equal it per two threads (run within one module of course).

Edit: The purpose of CMT is probably to get a more consistent scaling with the second thread per core than SMT. I also believe that the figure 80% is more likely to happen with a server workload than a desktop workload. That would also explain why the desktop test are lacking in performance compared to Thuban in MT.

[Opteron146]

It's hard to forget something I've never noticed. Anyway, as you say that list is gone now so I have no idea how accurate it was.

Edit: A bit like saying that there will be only one Interlagos model at launch, because the same site lists only one model:

http://www.shopblt.com/cgi-bin/shop/...er_id=!ORDERID!

shopblt was only 1 source, there were 4-5 other shops, which back-uped the lineup of 3 models.
Now concerning your Interlagos example, that does not fit, because it is another segment. The retail segment of server CPUs is very, very small. If there is demand for an Opteron, than people buy a complete machine+service and don't do a "DIY-build" of the server in their basement.
Therefore, most shops do not have any Opterons, some only have a few. Furthermore, there is no other shop which could back up that fact.

Anyhow, we have confirmation now:
amdfxpressdeck10adhfx57.jpg

[-Boris-]

People who says that AMD wouldn't be able to add two cores to Phenom II and rise frequencies at the same time. Consider this:

Agena 4C 2.6GHz 2Mb L3 65nm
Thuban 6C 3.3GHz 6Mb L3 45nm

Thats 50% more cores, 27% higher frequency and 200% more cache, and still cooler than Agena. Of course you can't just extrapolate this gains into 32nm, but I think it's reasonable to say that we would be able to see 33% more cores, higher frequencies (even more with turbo) and an extra 2Mb cache and still have a smaller chip than Thuban. Throw in some core enhancements and you're set.
Would it be as competitive as BD? Maybe, maybe not, but I think it's a bad sign when you first really new architecture in 12 years isn't clearly a better choice than the old one. Intel did this once, they crippled their old P6 in favor for Pentium 4 a century ago, it turned out that then the improved P6 came back 5 years later it was twice as fast as their current Pentium 4, and that's dual vs. dual, their P6 derived architecture had more thermal room for extra cores and came as C2Q delivering even more performance.

Well I think even a beefed up high frequency 4C/6C Phenom III with doubled FMAC capable FPU and better prefetchers.would actually perform better against Intels quads than BD will considering the leaks and price. But AMD made the choice to focus on cores to make it an Apples to Oranges comparison they could benefit from. I think it's their server focus that makes them do bad desktop processors, in server world multithreading is everything.

[liberato87]

has anyone taken a look at this?

http://www.donanimhaber.com/islemci/...onuclari_1.htm

It seems "official" Amd slides...
some people post ONLY the cinebench slide, because fx seems to perform worse than i7 2600k and similar to i5 2500k, but take a look at the other slides.

[Opteron146]

Thats 50% more cores, 27% higher frequency and 200% more cache, and still cooler than Agena. Of course you can't just extrapolate this gains into 32nm, but I think it's reasonable to say that we would be able to see 33% more cores, higher frequencies (even more with turbo) and an extra 2Mb cache and still have a smaller chip than Thuban. Throw in some core enhancements and you're set.
Would it be as competitive as BD? Maybe, maybe not, but I think it's a bad sign when you first really new architecture in 12 years isn't clearly a better choice than the old one. Intel did this once, they crippled their old P6 in favor for Pentium 4 a century ago, it turned out that then the improved P6 came back 5 years later it was twice as fast as their current Pentium 4, and that's dual vs. dual, their P6 derived architecture had more thermal room for extra cores and came as C2Q delivering even more performance.

Fair comparision, but with a brand new architecture the important point is the 2nd or even 3rd generation. The first one is very often buggy and not well optimized. Intels very first S423 Pentium4 was crap, the Socket 478's Northwoods were quite good, but then Preshott was the end, because they could not control the power consumption, and the pipeline got ridiculously long.

I do not see these problems here, the only problem is low-IPC, and a still not well running process at GF. Both could be fixed in the next revision. Then you still have superiour clocks. One should not forget, that Llano's CPU part @32nm is neither running well. Only ~3GHz clock, with OC you can reach maybe 3.6, Bulldozer seems to reach easily 4.8Ghz, with 8cores... and it has AES, AVX, SSE4.1/4.2... IMO really the better option to have build Zambezi, especially if the next revisions will gain some IPC.

[-Boris-]

Looks fake in design, it's nothing professional about it. But the numbers look real, game benches are clearly GPU limited and the rest is hand picked FMA4 with cut Y-axis. Looks like official charts since they try to hide performance disadvantages.

[LightSpeed]

These leaks are useless, most are surely crippled and they mean nothing. However, the pricing does seem official and points to BD performing very close to the level of a 2600K in MT apps. If it overclocks well, its all good. I also believe the release date being very near, most likely two to three weeks at max from now.

[liberato87]

Looks fake in design, it's nothing professional about it. But the numbers look real, game benches are clearly GPU limited and the rest is hand picked FMA4 with cut Y-axis. Looks like official charts since they try to hide performance disadvantages.

I dont know if these are true or fake.. I assume that they re fake, unitl we have a confirmation.
Ok game benches are gpu limited but full hd is the resolution that gamers use most.. so I dont care about benches in 1280x1024 only to see the best cpu, useless IMHO.
what about multithread slide?

[dess]

Would recommend taking a look at this one, as well...

amdfxpressdeck_12a_dh_fx57.jpg

Nothing points that way. Llano which is harder to produce isn't affected at all.

Isn't affected at all!? Then why it is in short supply? While they're concentrating on these as being mainstream parts they face the biggest demand here.
Then, most Orochi dies that produced are going to server OEM's and Cray, as Interlagoses and perhaps Valencias, at much higher profit margins than desktop CPU's.

hand picked FMA4 with cut Y-axis.

No cut in that diagram, base is at 0. And why hand-picked is 15 different kind of tests?

[AKM]

Meh, I was hoping for an advantage in multithread over the 2600K at least, this is mediocre performance.

[-Boris-]

Fair comparision, but with a brand new architecture the important point is the 2nd or even 3rd generation. The first one is very often buggy and not well optimized. Intels very first S423 Pentium4 was crap, the Socket 478's Northwoods were quite good, but then Preshott was the end, because they could not control the power consumption, and the pipeline got ridiculously long.

I do not see these problems here, the only problem is low-IPC, and a still not well running process at GF. Both could be fixed in the next revision. Then you still have superiour clocks. One should not forget, that Llano's CPU part @32nm is neither running well. Only ~3GHz clock, with OC you can reach maybe 3.6, Bulldozer seems to reach easily 4.8Ghz, with 8cores... and it has AES, AVX, SSE4.1/4.2... IMO really the better option to have build Zambezi, especially if the next revisions will gain some IPC.

But brand new architectures isn't usually worse or equal to the old, compare K7 to K6, K8 to K7, Core i7 to Core 2, Core 2 to Core, the only example of this is the failed P4 architecture. See the pattern? And your comparison with Llano is unfair. It has low stock clocks because it has a full 400 shaders eating power, and at the same time it isn't meant to be high performance. And you can't compare overclocking either, Llanos bad overclocking abilities is due to lack of dividers and frequency locks. An unlocked Llano without graphics part would overclock much much better.

[liberato87]

Meh, I was hoping for an advantage in multithread over the 2600K at least, this is mediocre performance.

I think you have to consider that FX-8150 is 245 $ and i7 2600k is over 300$.
I dont think it is mediocre, I think it is a balanced cpu, with that price it should be a cpu between i2500k and i7 2600k, and from these slides it seems to be compared like that.

[Lightman]

Based on these slides it is a good step in the right direction! Not a leap forward but a solid step up.

With that performance I won't be disappointed. Plenty of knobs to turn and keep me entertained with new BD CPU coming to my system ;].

Can't wait really because 3 days ago I've sold my 1090T and temporary putted X2 555 in it's place. I was shocked how much slower this CPU is in games even @4GHz compared to 1090T. In Crysis2 FPS cut in HALF! Civilization 5 visibly slower, even EVE Online is jerky now! Game engines are definitely going in the right direction with MT support

[-Boris-]

I dont know if these are true or fake.. I assume that they re fake, unitl we have a confirmation.
Ok game benches are gpu limited but full hd is the resolution that gamers use most.. so I dont care about benches in 1280x1024 only to see the best cpu, useless IMHO.
what about multithread slide?

Game benches which are not GPU limited are relevant, because you can see which processor which will be bottlenecking first in future games. That both a P4B 2.4GHz and Athlon X2 at 2.4GHz is able to get the same result in a GPU limited Q3 bench doesn't mean they perform the same in Crysis.

Isn't affected at all!? Then why it is in short supply? While they're concentrating on these as being mainstream parts they face the biggest demand here.
Then, most Orochi dies that produced are going to server OEM's and Cray, as Interlagoses and perhaps Valencias, at much higher profit margins than desktop CPU's.

GF isn't in full 32nm production yet, a large part of their capacity is still 45nm. And Llano is mostly laptop, and I don't have a hard time finding those. Nothing unusual for an AMD node transition. AMD can't have a large 32nm production so short time after the transition. At least the last 4 node transitions has been low volume the first months. Well 45nm went unusually fast. But 65nm, 90nm and 130nm was low volume for several month before they had transitioned to full capacity on the new node.

No cut in that diagram, base is at 0. And why hand-picked is 15 different kind of tests?

You're right, my mistake. And it's 15 different tests, but not different kinds of test. It all measures FMA4 performance, which is unfair against SB. So still handpicked.

I think you have to consider that FX-8150 is 245 $ and i7 2600k is over 300$.
I dont think it is mediocre, I think it is a balanced cpu, with that price it should be a cpu between i2500k and i7 2600k, and from these slides it seems to be compared like that.

But I feel AMD with it's better multi core performance inflate the total score across the board compared to i7 and i5. So even if it perform worse than i5 in say games they're still more expensive since benches show them faster in other areas.

[haylui]

I think you have to consider that FX-8150 is 245 $ and i7 2600k is over 300$.
I dont think it is mediocre, I think it is a balanced cpu, with that price it should be a cpu between i2500k and i7 2600k, and from these slides it seems to be compared like that.

the world+dog hope that AMD could make something faster than Intel and sell dirt cheap.