AMD Zambezi news, info, fans !

[chew*]

Who pissed in your Corn Flakes this morning? For the majority of us, this is inconsequential. So a cheery picked sample can run 8.4Ghz? We still don't know how this thing performs under air or water for the average enthusiast.

I would not go as far as to say cherry picked. I blind pulled with no windows testing 24 chips based on there VID, the 4th chip we tested (note not a pretested ever chip ) did 8.4

We still had twenty chips left to try out but really didn't care after the 4th one.......

[Manicdan]

^proof that in the next 6 months we will be bombarded with world record breaker news.
i suggest we just have one thread with "record of the day" and just watch the numbers climb.

[EnJoY]

If you are going by AMD's marketing term for a "core" in Bulldozer, than yes, Thuban will undoubtedly outperform Bulldozer core for core. However, if you go on module vs core, which AMD quad module should outperform thuban six core in all situations. And it should be relatively close to Sandybridge quad-core, but SB will be faster clock for clock by about 10-15%.

My opinions only...

[drfedja]

Was a P4 slower than a P3 ? Sometimes no, sometimes yes, depending on the software. The absolute performance is not something so important for AMD. The most important thing is money. And just money. Spending gazillions dollars in R&D to reach the performance of a CPU sold in very low quantities (and generating very low incomes) like the 990X is ridiculous. Bulldozer must solve two problems : 1/ Be able to gain performances (with frequency increases) at mid-term without spending more gazillions in another µarch 2/ Compete with Intel *mainstream* CPUs (and not Extreme CPU) with a similar price/performance ratio.

I agree. But, in BD architecture are less tradeoffs than Netburst.

High raw throughput for an FP unit is nice. But in order to use this power in real-world application, you need a frontend able to feed it correctly.

Average IPC of most workloads isn't much more than 1 IPC on Thuban core. 4-way front end is more than enough to feed two threads.

And keep in mind the horribly slow L1 Write-Through, probably added in order to remove a bottleneck in frequency scaling. Write-Through means your writing from the frontend to the L2 "through" the L1.

No, that doesn't mean WT.
Write Trough means that every write to the cache causes a synchronous write to the backing store. Because L2 is slower than L1, L1 must wait for L2 to write out data. But there is WCC (Write Coalescing Cache) to hold on data for later writing out. I can't see why the WT policy cache is so much issue with BD core. Ratio between loads and stores is arround 2:1. For every two loads, we have one store.

So, seen from the frontend, the L1 write bandwidth is as "slow" as the L2 write bandwidth.

Not quite, because of WCC.

The last µarch to use that horrible trick was Netburst, with high frequencies in mind. Bulldozer comes with a L1 WT too and that point only could explain many disappointments from a performances point of view.

Again, I don't think so there is the problem with WT. L1D is WT, WCC is write buffer, and L2 is probably WB. Because of WCC there can be some issues with multiple write out streams. Also, we don't know what is behaviour of WCC when two integer cores writing data. There is probably WCC cache trashing.

[EnJoY]

If you are going by AMD's marketing term for a "core" in Bulldozer, than yes, Thuban will undoubtedly outperform Bulldozer core for core. However, if you go on module vs core, which AMD quad module should outperform thuban six core in all situations. And it should be relatively close to Sandybridge quad-core, but SB will be faster clock for clock by about 10-15%.

My opinions only...

[drfedja]

Was a P4 slower than a P3 ? Sometimes no, sometimes yes, depending on the software. The absolute performance is not something so important for AMD. The most important thing is money. And just money. Spending gazillions dollars in R&D to reach the performance of a CPU sold in very low quantities (and generating very low incomes) like the 990X is ridiculous. Bulldozer must solve two problems : 1/ Be able to gain performances (with frequency increases) at mid-term without spending more gazillions in another µarch 2/ Compete with Intel *mainstream* CPUs (and not Extreme CPU) with a similar price/performance ratio.

I agree. But, in BD architecture has less tradeoffs than Netburst. I expect per module min. same level of performance of K10, not 40-50% lower. Look at horrific chineese results of wprime. It is 65% slower than Thuban core per core and per clock. Something is wrong here. I still can't believe that it is true.

High raw throughput for an FP unit is nice. But in order to use this power in real-world application, you need a frontend able to feed it correctly.

Average IPC of most workloads isn't much more than 1 IPC on Thuban core. 4-way front end is more than enough to feed two threads.

And keep in mind the horribly slow L1 Write-Through, probably added in order to remove a bottleneck in frequency scaling. Write-Through means your writing from the frontend to the L2 "through" the L1.

No, that doesn't mean WT.
Write Trough means that every write to the cache causes a synchronous write to the backing store. Because L2 is slower than L1, L1 must wait for L2 to write out data. But there is WCC (Write Coalescing Cache) to hold on data for later writing out. I can't see why the WT policy cache is so much issue with BD core. Ratio between loads and stores is arround 2:1. For every two loads, we have one store.

So, seen from the frontend, the L1 write bandwidth is as "slow" as the L2 write bandwidth.

Not quite, because of WCC.

The last µarch to use that horrible trick was Netburst, with high frequencies in mind. Bulldozer comes with a L1 WT too and that point only could explain many disappointments from a performances point of view.

Again, I don't think so there is the problem with WT. L1D is WT, WCC is write buffer, and L2 is probably WB. Because of WCC there can be some issues with multiple write out streams. Also, we don't know what is behaviour of WCC when two integer cores writing data. There is probably WCC cache trashing.

[m411b]

chew* is there any video of any of the air/water testing you did?
Or if anyone else has any, post it up. I can't seem to find it any where.

[Evantaur]

I am a bit lost in this translation, especially with what it says at the end of that sentence. Does it mean that B2 stepping was just a testing one and there is going to be a different one for the final production (B2.G rumored plus there is no revision shown on that CPU-Z shot)? Or is it just an imperfection in Google Translator? Anybody from Finland to shed some light on it, please?

no, these were B2 ES

[AKM]

84159431.png

[Manicdan]

chew* is there any video of any of the air/water testing you did?
Or if anyone else has any, post it up. I can't seem to find it any where.

hardocp has a 13 minute video with a little water testing in there

[repman]

84159431.png

[FlawleZ]

84159431.png

B50 @ 3.3Ghz is way off. 2.83 pts?

I get better than that with 3 cores on my 720 BE.

[undone]

84159431.png

[Sarcasm]When I see these diagrams and the-like I always add some % on amd side because the poster is famous amdhater XXX[/sarcasm]

[Dumo]

Saw on youtube.....5.89Ghz 8c/8t @ 1.63Vcore SS -30C idle stable....nice

[xsecret]

Again, I don't think so there is the problem with WT. L1D is WT, WCC is write buffer, and L2 is probably WB. Because of WCC there can be some issues with multiple write out streams. Also, we don't know what is behaviour of WCC when two integer cores writing data. There is probably WCC cache trashing.

WCC is a joke in the current BD implementation and is not able to catch up with the massive loss that comes from the L1D. The entire caching-system is lowering the performance of the µarch. The L3 is a non-inclusive victim cache (L2 data are evicted to the L3) with data transfered from L3 to the L1D of the expected core without being copied to the L2. That mean high snoop traffic in order to keep the coherency correct. And snoop traffic is something really unwanted from a bandwidth/performance pov. There is a pardox here : The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

84159431.png

Bullsh1t.

[Formula350]

AMD FX CPU inducted into Guinness Book of World Records

A longtime favorite of performance enthusiasts and overclockers around the world, AMD (NYSE: AMD) today announced it has achieved the Guinness World Record for the “Highest Frequency of a Computer Processor,” by overclocking the upcoming 8-core AMD FX desktop processor. The AMD FX CPU, set to launch in the fourth quarter of 2011, achieved a top speed of 8.429 GHz, surpassing the previous record of 8.308 GHz. The record was set on Aug. 31, 2011, in Austin, Texas, by “Team AMD FX,” a group comprised of elite overclocking specialists working alongside top AMD technologists, who will also be named in the Guinness World Records.

Permanently in the record books

[informal]

The result above is from the guy whose name shall not be mentioned . I guess by what xsecret wrote the result is BS and maybe even too high for Zambezi

[Olivon]

The result above is from the guy whose name shall not be mentioned . I guess by what xsecret wrote the result is BS and maybe even too high for Zambezi

Yes and 2600K and 990X scores are too low for sure ...

[xsecret]

84159431.png

Where does that come from ? Core i7-2600K : 6.83, not 6.23. I7 990X : 9.22 and FX-8150 is much lower than that... or I missed something.

[Dimitriman]

100 Pages, grats!

[m_jones_]

I'm really happy about the overclocking, better get my watercooling set up running again.

[Olivon]

My guess is that FX-8150 is around 5.9-6.0pts on Cinebench R11.5

[Megacharge]

And losing customers in the process. Sounds like a sweet plan to me.

Not really, I'm sure a lot of Intel customers would run back to AMD.

[rog]

84159431.png

2600k score too low. It should be around 6,90 points. So this is not really a serious slide.

[Manicdan]

Not really, I'm sure a lot of Intel customers would run back to AMD.

this chip could be build around a whole lot of marketing to increase sales.
when someone looks at a laptop and sees for the same price that they can get more cores and more mhz with amd, they might not feel so bad with not buying intel. very few people really know performance and may never actually see real results, even 20% difference may not be noticed by an average user. what they do notice is noise and lag, and honestly you dont have those with 90% of the tasks people do. when it comes to gaming and rendering etc, they might not pick up on anything less than 20% different. i remember back when i7 first came out and i had people trying to say they have an 8 core desktop, not realizing they have ~4.5 cores. today they understand threads a little better and so AMD can try to stay away from being called 4c/8t while making sure that intel is still remembered that way.

a laptop say 2c/4t at 2.5ghz
vs a laptop that says 4c 3ghz
it sounds VERY tempting to buy the latter, because the math in your head thinks its 2x faster unless you read up on benchmarks.

the only catch is that AMD dosnt do marketing and we all know that