MACHINE-CHECK ARCHITECTURE
The IA32_MCi_CTL MSR controls error reporting for errors produced by a particular
hardware unit (or group of hardware units). Each of the 64 flags (EEj) represents a
potential error. Setting an EEj flag enables reporting of the associated error and
clearing it disables reporting of the error. The processor does not write changes to
bits that are not implemented.
NOTE
For P6 family processors, processors based on Intel Core microarchi-
tecture (excluding those on which on which CPUID reports
DisplayFamily_DisplayModel as 06H_1AH and onward): the operating
system or executive software must not modify the contents of the
IA32_MC0_CTL MSR. This MSR is internally aliased to the
EBL_CR_POWERON MSR and controls platform-specific error
handling features. System specific firmware (the BIOS) is responsible
for the appropriate initialization of the IA32_MC0_CTL MSR. P6 family
processors only allow the writing of all 1s or all 0s to the
IA32_MCi_CTL MSR.
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