MaximusIV-Extreme Thread

[Raja@ASUS]

To quote anand in your link:

Seems to me that anand is saying the SA voltage would control the IMC voltage, since they're in the same power plane.

Raja, is it possible my results were different than yours due to the D1 ES CPU I was testing with?

The core voltage for a functional unit is not the same thing as the transceiver IO or termination voltage for any associated signal line (unless engineered in such a way). It is the IO voltage that is important for overclocking as that drives the transceivers which receive and send data. Think of it as vIOH and VTT. The placement of the memory controller was never in doubt - my opening response said that it sits to the side but the interconnect will be driven by the IO voltage. The main thing here is to understand the role of IO.


I never used the D1s myself, there may be some differences but they would not be that large as to flip the role of the IO rail. Either way, I suggest you have another in-depth play with some boards and CPUs and see for yourself which voltage has the impact on memory clocking.

-Raja