MaximusIV-Extreme Thread

[miahallen]

Don't have any GBT boards here so can't say about what their boards do. VCCIO pretty much tells me what it is - IO voltage. The SA role is as an IO hub and the memory controller sits as a side unit (any interconnects will be driven by IO voltage)

Check here:

http://www.anandtech.com/show/3922/i...ture-exposed/4

Should add that on our boards my memory clocking results are all tied to VCCIO - and that's with Hypers running past DDR3-2100. On top of that remember the pin location for voltage rails is well stipulated - so the voltage labelling is correct.

-Raja

To quote anand in your link:

The System Agent houses the traditional North Bridge. You get a 16 PCIe 2.0 lanes that can be split into two x8s. There’s a redesigned dual-channel DDR3 memory controller that finally restores memory latency to around Lynnfield levels (Clarkdale moved the memory controller off the CPU die and onto the GPU).

The SA also has the DMI interface, display engine and the PCU (Power Control Unit). The SA clock speed is lower than the rest of the core and it is on its own power plane.

Seems to me that anand is saying the SA voltage would control the IMC voltage, since they're in the same power plane.

Raja, is it possible my results were different than yours due to the D1 ES CPU I was testing with?