Bulldozers first screens

[memmem]

same as any other operand. If it cannot be sheduled at the same cycle it will be sheduled the next cycle.

So if cpu 1 needs 6cycles for one AVX instruction it will need 7cycles to do 2 AVX ops


Also with FMAC BD can do 8. SB can do 12 if they are different types but that rate is not sustainable.

Thanks flyck.

What I am trying to say is:

* if there´s only 128 bits instructions in a workload than you can safely say you have 8 cores (Zambezi or SNB (4+4HT))

* if there´s 256 bits instructions, than maybe the CPUs will behave like a quad core.

Is it dumb?