AMD Zambezi news, info, fans !

[informal]

OK guys,now that we have almost all the details of the design with rumored clock speeds,IPC jumps,frontend penalties,Turbo clock information, I'm pretty sure the Donanimhaber slide is genuine . I have no idea if it was AMD who actually made the slide,but the speedups are matching almost exactly the numbers derived by various other sources on the net(rumorpedia's,scarletwh*re,server speed up slides for MT workloads).
Summary by me ,purely hypothetical of course (for a hypothetical 3.5Ghz Zambezi with 4.2Ghz integer turbo mode : ) ):

Single thread pure integer desktop workloads :
-around 12 to 15% IPC improvement -too complicated to explain how I got to this particular range ,
-around 13% effective clock improvement-4.2Ghz BD Turbo Vs 3.7Ghz Thuban Turbo,
-cumulative speed up of 30% versus Thuban in this type of workload,on average(can be higher or lower ,depends on application and whether it's ALU bound or memory latency sensitive)

Single thread fp workload(this covers in my opinion integer SEE too):
- around 40%-50% better per clock performance than one Thuban core;this is one 128bit FMAC/IMAC Vs one Thuban FP part of the core
-around 13% effective clock improvement-4.2Ghz BD Turbo Vs 3.7Ghz Thuban Turbo <-Turbo should kick in when single threaded workload is detected ,even if it is a floating point(power draw intensive)
-cumulative speed up of ~60% versus Thuban in this type of workload,on average.

Multi threaded integer workloads(SSE in MMX/IMAC pipelines):
-50-80% faster than Thuban 1100T

Multi threaded floating point workloads(fp ops in FMAC pipelines)
-50-80% faster than Thuban 1100T

All of this equates to a total of around 40-50% faster than Thuban 1100T @ 3.3Ghz. Or around 15-20% on average faster than Westmere 3.33Ghz 6C in client workloads.
I also think that the leaked AMD Terminator slide (FX,"I wil be back") is not without merit .