i5-2500K/2600K batch number and o/c results

[crossg]

If you look at the microarchitectural papers for Sandy Bridge(SNB) there's a decoded uOp cache which allows micro-ops to be cached off and allow the decode unit to be turned off if it isn't needed. This is rather important because for "smoke tests" like LinX and Prime95 try to keep very small loops that fit completely within the L1 instruction cache because historically execution units and caches are where most speed paths lie, so the harder you pound those units, the more likely you're able to destabilize the system.

However, it appears the caches and execution units in SNB are robust, so the weakness appears to be in the decode stage, which is rather complex for x86 parts. The uOp cache in SNB allows the decode stage to be turned off for tight loops, and any instabilities in the decode stage will only be exposed once you run a program that doesn't fit in cache and requires constant instruction decode like 3DMark.

I think there needs to be an amendment to SNB stability and that would be to run some sort of large program such as 3DMark, etc.

One problem with 3D mark is when your processor is unlocked it reports the wrong freq. I did two tests @ 5000 with my 2600K

3D Mark 11.

Vantage

Both reported CPU @ 3400.

Not sure what the 2500K reports.