Hit a 4Ghz wall @1.35v core shutdown, ideas?

[R37ribution]

you shouldn't have any speed step or Ce1 EIST or HT on, only turn those on after you've achieved a stable clock, that way you'll be able to determine where you went wrong easier and tweak around it with minimal confusion... also CPU PLL is way too high should be around 1.65 not 1.8 last i looked at bloomfields... Could you give us a bios update right now complete run down of your settings in a code window... That way we can better assist you with Overclocking, IOH was pretty high too... just reply to this with your New Settings ... also speed step would be why your getting 4GHZ not 4.2GHZ if the clock was fine tuning itself down by .5 ... which happens for my C2D chip occasionally .... just an idea... remember read through my first part about disabling features while OCin, once stable enable one by one

Late post lol! internets screwed up today

Really? Are you guys reading anything in this thread or are you just mindlessly replying to get your post count up? Not two posts ago in my last update you will find I have my setup passing 30 Linpack tests @ 4.2Ghz with SpeedStep enabled; its even in a code window. I'd say I've "achieved a stable clock" as you call it. Oh and I've had HT disabled since I reached 4Ghz. In the same post you overlooked I stated "My next step will be an attempt at enabling Hyper Threading... Or maybe the 4.5Ghz club".

1.8 is the default voltage for bloomfield cpus cpu pll. So find the system more stable at lower cpu pll volts even as low as 1.3v dont push it more then 1.86. 1.9 i think is MAX.

Owners of Gigabyte boards must all be oblivious to the fact that Asus board owners cannot lower the CPU PLL less than 1.81v and don't even have an option for QPI PLL. I'm trying not to sound too irritated about such comments since there were screen shots above from another Gigabyte board owner. He suggested a lower PLL weeks ago.

Asus owners have asked multiple times for QPI PLL to be adjustable and a CPU PLL that allows for lower voltage, we've even asked for at least a table that tells us what the QPI PLL gets set to as we adjust the CPU PLL

I appreciate constructive criticism as I am well aware that I have plenty to learn. Hell, I haven't even entered the realm of "CPU Differential Amplitude", "PCIE Frequency", "CPU Clock Skew", or "IOH Clock Skew"; however, replies suggesting the same thing that has previously been suggested and found not to be a possibility just tells me you're too lazy to even bother reading the thread.