AMD Cayman info (or rumor)

[BrowncoatGR]

If it is indeed a 4 port VLIW architecture this will be very expensive for AMD as i speculate they will have to recoup the R&D costs for moving the SI design from it's initial 28nm target to 40nm using just one derivative. This of course will allow them to finalize the design on a well known process before they move it to the murky waters of 28nm and therefore lower risk. I suspect we will see a 5770 replacement as a 28nm test vehicle as soon as the process is ready for production.

In Cypress (and back to R600) there were 5 SPUs (Stream Processing Units) per SP (Streaming Processor).
Like in the first image here: http://www.anandtech.com/show/2841/4
Now there will be 4 SPUs per SP. And as ajaidev points out, there may be a different arrangement of simple and complex units within the SP instead of 4+1.

If they keep a grouping of 16 SPs per SIMD, and there are 1920 SPUs, then Cayman will have 30 SIMDs per chip.

The reason for such a change might be to increase utilization. It could have good results if one or two of the units in your 5 wide design are usually sitting idle. That's why RV770 and Evergreen had such a huge difference between low utilization (games) and high utilization (furmark) in terms of power-draw and heat output.


They have had a 5-wide design for a while now. Why assume that's never going to change? Especially on a generational change?

Iirc to take advantage of all the the SPUs per SP certain scheduling conditions have to be met that makes it very difficult to even get close to the theoretical max performance with real world code