Quote Originally Posted by savantu View Post
Clear win indeed. The higher you go in power the bigger the gap between Bobcat and Atom. Conversely, the lower you go, the opposite happens, until Bobcat can no longer compete ( sub 5w ).



So now we're moving from CPU power to core power. What's next ? They'll put forward FPU and ALU power ?
If an APU has disabled everything else except one core and the IMC, by using power gating technology, you should not have a difference compared to the single core.


Well, none. Because they know they can't. Which also means they know it is not "sub 1 w capable" , at least in its current generation.



And you're telling me the core burns sub 1w and the IMC is over 2w ?



So according to you, memory I/O is the main culprit for high power consumption.
"the use of .5v DDR3 will incur a power adder"

If standard DDR3 will change the TDP by an amount worth mentioning (perhaps 1-2w) then yes, the DDR3 IMC likely does contribute over 2w.

I would have though that was common knowledge to you anyway.

As Hans said, a lower spec, lower power DRAM interface would be used if the core ever made its way into devices that sensitive to power draw.


By the way.