Quote Originally Posted by JumpingJack View Post
The oc'ability limit is no doubt due to increasing complexity and the drive for higher integration. Moving the GPU, PCIe, and most of the northbridge components into the CPU socket it becomes more practical to derive all those buses and components from a common clock.

The real OCability limiter here is not the clock generator or the CPU for that matter but the tight tolerance (or intolerance if you wish) of the PCIe bus, since that now derives its clock from the same that drives the CPU and others, it would not take Einstein to predict that OC will be limited.
why cant a PLL fix that? nehalem is a highly modular design which is why every core, mem controller, and the uncore have their own PLL. everything is decoupled to provide flexibility.

it doesnt take an einstein to fix this problem. aside from that einstein would more likely avoid problems in the first place rather than fix problems.