AMD's Bobcat and Bulldozer

[-Boris-]

HMm, where is the 64kB L1I$ in your Decode/Prefetch area ?
I would say the big area, left in your blue part would be the L1I$. With 64kB it has to be the biggest part in any case ...

Already noted that, and made a revised pic.

What's up with different L2 cache sizes and sizes of the cores? The chips on top seem to have some extra logic?

EDIT: L1 Instruction cache is in the cache part of the green field.