AMD's Bobcat and Bulldozer

[informal]

Westmere vs Nehalem, Thuban vs Deneb.
Three of them got turbo, one doesn''t.
Doesn't that give Thuban a bit too high performance increase, which affects the calculated BD performance increase? Just asking..

Nope,i wrote the quote from the article:

This is verified in practice as, at equal clocks, the average gain between the Phenom II X4 955 and the Phenom II X6 1090T is 24.7% (23.9% without Turbo CORE). The performance gain on the Phenom II X4 965 is a notable 18.2%.

The difference is less than 1%.

[Donnie27]

it's clear they are not

I said the same, not the same size. The top ones look like they have the memory controllers and the bottom ones connect to them, could easily be wrong but so what? The Die shot looks like Left and Right mirrored instead of Top and Bottom. Half of the processor would be left and or right, not top and bottom.

[-Boris-]

First thoughts on the layout.

EDIT:
Should be L1 cache in the orange field. L2, L3 and other stuff was so obvious so I didn't mark them.

, Green field shall say "Prefetch!"

[-Boris-]

So this is the 8 core (4 module) BD fusion chip?

http://www.techeye.net/chips/amd-sho...ks-more-fusion

Not Fusion, only CPU in this one, this is Bulldozer.

[informal]

The top 2 modules are a bit larger indeed.

[Opteron146]

First thoughts on the layout.

HMm, where is the 64kB L1I$ in your Decode/Prefetch area ?
I would say the big area, left in your blue part would be the L1I$. With 64kB it has to be the biggest part in any case ...

[-Boris-]

HMm, where is the 64kB L1I$ in your Decode/Prefetch area ?
I would say the big area, left in your blue part would be the L1I$. With 64kB it has to be the biggest part in any case ...

Already noted that, and made a revised pic.

What's up with different L2 cache sizes and sizes of the cores? The chips on top seem to have some extra logic?

EDIT: L1 Instruction cache is in the cache part of the green field.

[informal]

All above differences in the chip are easily doable via solid knowledge of certain imaging software ,and that's what AMD did.

[Mechanical Man]

Better picture page 20 : click

There u can clearly see those are of different size.

[JF-AMD]

8-core Orochi die. Heavily photoshopped. We don't release the final shots until launch.

[Opteron146]

What's up with different L2 cache sizes and sizes of the cores? The chips on top seem to have some extra logic?

I hope Hans will enlighten us soon

Until then, my wild speculation about the different core sizes:

• (real) 256bit FPUs plus smaller but faster and leaky 6T L2 cells on the top
• 128bit FPU, with bigger, but less leaky 8T L2 cells on the bottom.

But this is just my amateurish guess .. ;-)
Also just red a paper which stated that 8T cells are smaller than 6T cells in 32nm

I would say the FPU is in the middle of your two orange parts. Otherwise the FMAC part on the bottom is imo too small .. that should be two 128bit FMAC Units, they have to be bigger than the one INT cluster/core.

@JF:
Of course it is photoshopped, but you wouldnt change the module sizes, wouldnt you ?

[informal]

^^ They would

[-Boris-]

^^ They would

Far more probable than 2 different types of BD modules on the same die.

We don't know about L2 and L3 cache sizes yet do we?

[informal]

Far more probable than 2 different types of BD modules on the same die.

We don't know about L2 and L3 cache sizes yet do we?

We know very little as it seems . Too much of the good stuff was omitted for a good reason.

[Opteron146]

^^ They would

Ok, maybe some scaling .. but the top cores are not scaled, there is definitly more in it, thus, if this is added just by photoshop, then it would either not be an Orochi die, or Zambezi / Valencia are not based on that Orochi die, as I though earlier.

Then Orochi maybe would be just some kind of strange prototype.

We don't know about L2 and L3 cache sizes yet do we?

JF stated in his first version of his latest blog entry 2MB L2, this and the Open64 Compiler info let me believe that it is really 2MB.

[Sn0wm@n]

top half looks like a GPU with cache, but orochi was supposed to be a 4 module 8-core without GPU

we never knew more then the few tidbits and jf-amd did say that we have alot to know more about bulldozer ... so maybe its a gpu ... maybe not ... who knows really besides the engineer at amd

[Mechanical Man]

Lol, why would there be GPU?

[slaveondope]

Noob statement/question warning

Would it be completely out of the picture for them to start integrating some parts of a "gpu" onto bulldozer not for vga but for the benefits of (my mis/understanding) improved fpu calculation speed or whatever "fusion" of gpu and cpu is suppose to bring

[Sn0wm@n]

Lol, why would there be GPU?

ati stream supported programs would benefit ... like powerdvd10 for example


http://www.cyberlink.com/products/po...iew_en_US.html

[Mechanical Man]

But there is no point to waste die space for so limited benefit.

[JF-AMD]

There is no GPU in Bulldozer at this point. That could always happen in the future but not for the products that we are launching in 2011.

[-Boris-]

I suppose that the predecessor to Llano might have BD-modules instead of K8 cores.

[[XC] Oj101]

John, I know you don't really comment on desktop hardware but can you confirm whether the desktop parts will be almost a year after server CPUs?

[Oliverda]

to JF: Is there any chance to have a 6 module Bulldozer die at 32nm in the future?

[-Boris-]

to JF: Is there any chance to have a 6 module Bulldozer die at 32nm in the future?

I think he said a couple a pages ago that there was no plans for that at this point on 32nm.