AMD's Bobcat and Bulldozer

[nn_step]

It's 32bits Fetch

Given that Phenom has a 32 BYTE pick buffer and a 408bit fetch, I see that has highly unlikely.

Added to the fact that Bobcat has a 22 byte decode

BD 2 was not all around new since it's naturally based on the BD 1 version that was supposed to come out at 45nm. I suspect that like in the case of Barcelona,they were power limited at 45nm and perfromance was not up there where they wanted .So they went with an improved core,done on a smaller node and delayed it 2 years(2009->2011). This gives them more room for improvements at the core level and more clocks ,all within the same power envelope.I expect 15-20% in core level improvement + 30% in clocks.



Its 4+1(branch fusion supported) decoder at the front end,with a so called "accelerate mode" if certain conditions are met.AMD is not disclosing anything about this particular feature ,but essentially this increases the decode rate by some unknown factor.

But without more details, optimizing the decode rate is impossible.

For example, can a single thread take up the entire decode unit for a couple clock cycles if the other thread is sleeping?

So, not to talk out of school, but I did ask one of our design engineers about the ability of the shared front end to keep two integer cores fed and he had absolutely no concern because of things that are done to improve the front end.

Can't say any more beyond that because a.) it is not public info and b.) I don't really know enough about how those things work to accurately describe them.

In my mind this is not a concern of the engineering team. After all it is a completely new design. If they had taken the front end off of an existing product it might be more of an issue, but as I understand it, that has not happened.

Could you find out if the threads share a pick buffer or if it is shared.
and if so, what size(s)