Quote Originally Posted by Calmatory View Post
1. Deeper pipeline. -> Higher clocks.
not if the delay per stage stays the same. longer pipelines also tend to lead to lower ipc.
2. 32 nm Gate Last HKMG SOI. -> Higher clocks.
not really.aside from that very little is known about their 32nm process while everyone else has released their info at iedm 09. there are some rumors that it isnt looking to good. supposedly they are using their 45nm metal stack for almost every layer.

also gate last is inferior to gate replacement integration. in gate replacement you can optimize both pmos and nmos transistors. the problem is that intel has patented a lot of ip with respect to HK/MG. i dont know if glofo wants to license intel's patents.