Am I the only one who noted that Anandtech wrote "Bulldozer CPUs will be AMD’s first 32nm processors manufactured at GlobalFoundries."
That can't be right, or have Bulldozer been pushed ahead of Llano?
Am I the only one who noted that Anandtech wrote "Bulldozer CPUs will be AMD’s first 32nm processors manufactured at GlobalFoundries."
That can't be right, or have Bulldozer been pushed ahead of Llano?
45nm BD was not on any roadmap. So i guess it's seem so normal to us, that it's not to be noticed.Originally Posted by marten_larsson
Yeah, you're right. That's a mistake. Llano will be the first one
The person who said it actually said the word "server" in that statement. Especially because he has no idea what the llano schedules are.
Earlier JF said that there was a plan for a 45nm BD with DDR2 support which should have come in ~2009.
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never got this information.
Yes, BD was originally planned to been launched at 45nm, a while after Phenom II. I don't know the reason to the delay, but AMD said they would use the extra time to enhance Bulldozer even more. Could be that they learned the importance of having a node capable of a large chip before manufacturing it, since they released Agena on a node too early. Just like GTX 280 and GTX 480 from nVidia.
If BD doesn't work with current AM3 boards, why not start all over with a new socket? This would give them several options even though they can't be combined all together:
- Integrated PCIe, LGA, use the same socket as Llano, just to name a few.
All they got now is a new socket that works with old CPU's, not the other way. But yet another socket change is inevitable as soon as they want to add one of those features, like PCIe for instance.
AM3r2 seems like a bad compromise, unlike AM2+ and AM3. It's not a completely new socket by 2011 standards, and will be replaced too early because of that. And it forces BD buyers to get a new board since AM3 doesn't work.
If this years 870 - 890FX-series boards had been AM3r2 then it would have made sense, now it doesn't. I can't think of a reason why they weren't.
Pointing out that AMD wants to make money doesn't explain it, since the whole idea behind the AM series is to make older boards work with new CPU's..
I think the issue with the motherboards is the more advanced power gating features in BD,on a module level inside the chip. It is kinda bad for present users to be unable to just buy Zambezi and slide it in their AM3 boards.But ,one can buy AM3R2 board later this year,when they appear ,and just use the X4/X6 until Zambezi comes along. Who knows,maybe Zambezi will even support 4 channels of memory too.
http://www.tomshardware.com/reviews/...ps,2724-4.html
http://www.techreport.com/articles.x/19514/1Thus, you can expect to see Bulldozer-based CPUs dropping into existing server boards and, likely, Socket AM3 desktop platforms as well.
I think bulldozer should be like PhenomII X6,compatible with AM3,but won't work with all AM3 broads.AMD says Bulldozer-based chips will be compatible with today's Opteron sockets C32 and G34, and we expect compatibility with Socket AM3 on the desktop, as well, although specifics about that are still murky.
Last edited by mindfury; 08-25-2010 at 06:34 AM.
The new server board for MC systems are built with the new electrical specs in mind(sockets G34 and C32). Socket AM3 wasn't(just like the socket F wasn't and it got replaced with C32-same pin count as socket F!!!). That's why we have a R2 version of AM3 that adds new features needed for power gating in Zambezi.
But yeah,we should wait and see how this plays out.
Socket F was introduced in 2006,only support DDR2,it has to be replaced.
Socket AM3 is not Socket F.
not if the delay per stage stays the same. longer pipelines also tend to lead to lower ipc.
not really.aside from that very little is known about their 32nm process while everyone else has released their info at iedm 09. there are some rumors that it isnt looking to good. supposedly they are using their 45nm metal stack for almost every layer.2. 32 nm Gate Last HKMG SOI. -> Higher clocks.
also gate last is inferior to gate replacement integration. in gate replacement you can optimize both pmos and nmos transistors. the problem is that intel has patented a lot of ip with respect to HK/MG. i dont know if glofo wants to license intel's patents.
if AM3+ is due out so soon, sounds like its really not that big of a deal if BD dosnt go to older client sockets,
honestly you can keep your ram, bring your AM3 cpu forward, and when BD comes out, it wont be a question of how dumb a reviewer was to compare BD to SB using older sockets with missing features that would be super important to BDs efficiency.
i hope im not the dumb one for thinking that BD was coming out before AM3+, lol.
Socket F accepted Istanbul cpus just like AM2+/AM3 accepts Thuban.AMD could have opted for an F+ and make it Lisbon only compatible ,but they opted for a pin compatible C32 socket that has a new spec. for BD support. What AMD fellow engineer said in the pre- Hot Chips briefing is that the AM3 boards are not electrically compatible with BD cores due to new power management incorporated in the new uarchitecture(even though the new socket will accept the old chips).
IMHO still there is a chance for the present AM3 mobos to support the BD but probably you will loose some power management related feature.
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I got that part, but it still doesn't explain why AMD didn't launch the AM3r2 socket this spring.
They could add all the power gating features for G34 (launched in march) and C32 (june), but not launch AM3r2 with 800 chipsets in april. Lame.
I see absolutely no reason for this, just look here at XS where lots of users bought a X6 and a 800 board with the intention to upgrade to BD when it shows up.
If this upgrade path suddenly needs yet another board for BD, which also happens to show up at least 6 months later than SB, there's no reason to stay with AMD from a economical point of view.
You need a new board either way.
I think you have been frightened by Netburst for a long time.
In fact IPC have no direct relationship to the length of pipeline.
I don't care about any of the power management features. My system Folds 24/7!Just give me a socket AM3 pin compatible BD.
As quoted by LowRun......"So, we are one week past AMD's worst case scenario for BD's availability but they don't feel like communicating about the delay, I suppose AMD must be removed from the reliable sources list for AMD's products launch dates"
If only 1 core in a module is used, will it operate at 100% then ? only dropping to 90% per core if both cores are active. IE 100% with 1 core, 180% with 2 cores.
As far as i can see JF only posted the 180% figure based on total throughput, all cores being used. He has'nt disclosed any performance for a single core being used on a module (I havent seen this info anywhere).
There is alot of confusion on this issue, alot of which also seems to compare it running 80% compared to a K10.5 core, which makes no locical sence.
A comparison of this would seem more fair.
1 BD core(single module) vs 1 PhII core, clock the speed of these to match same performance. Can compare mhz/power or what ever is aproprite.
2 BD core(single module) vs 2 PhII cores, can be clocked to match same performance to compare mhz/power as above, or use the previous results to see how many % performance drops by using both cores on a single module.
Last edited by EvilOne; 08-25-2010 at 07:24 AM.
No, it's not like that. They will run at 100 % each, either one or two cores.
It's all about the module who will have the performance that's 180 % of two regular full cores (2 x 100 %), but the size is much smaller than two regular cores.
Slides say single thread performance is higher the current P2, but that doesn't mean its IPC is higher.
I dont think that's correct. They are based on shared resources, so using 2 instead of 1 will have 'some' impact.
2 Modules using a single core each, should perform better then 1 module using 2 cores, unless im getting something totally wrong with this new arcutecture.
PS excuse my spelling i was taught english in a school in england lol, thus i cant spell to save my life.
Which is what i tried to compensate for in my example. It takes the IPC out of the equasion as both cores are clocked to aprox the same performance before you compare the impact of the 2nd core being used in a single module. I wasnt trying to compare a P2 core with a BD core.
Last edited by EvilOne; 08-25-2010 at 07:34 AM. Reason: typo
You have a total of 4 instructions executed by each integer core.In 10h you had a total of 3(be it mem or math ops).That's a 33% difference.Now count in the massively improved prefetch and other stuff in the front end that are supposed to keep the core(s) busy all the time and you have a potentially pretty nice boost in IPC. Remember that with 10h ,the 3ALUs were paired with AGUs and sat around just waiting for data doing nothing. The new 2+2 scheme is built in order to address the under-utilization.
2 ALUs per core is somewhat disappointing. I guess instead of developing some technological trick (that would take die space and power) to increase the efficiency of underutilized units, they just took them out. It's probably a big boon for power efficiency, but it leaves IPC up in the air.
On the face of it, taking out ALUs seems like it would reduce IPC. But since IPC rarely goes past 2 on average that might not be the case. The branch prediction, prefetch, decoders, reorder, and caches sound nice. If they could utilize these units to keep the remaining ALUs + FPU fed a larger percentage of the time IPC could still go up significantly.
Considering the reduced ALUs and shared units, it sounds like BD will be a very power efficient architecture. Couple that with a long pipeline, aggressive prefetch, etc and there may be major headroom for turbo/OC. Though, if the rumors are true, they may need a new process to realize it's full potential.
As for single-threaded versus multi-threaded. Low ST performance would affect office users and gamers (slightly). But as a power user I won't be affected because in low thread situations I just run more programs. Servers and HPC sound like they would be serviced by this chip well.
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