AMD's Bobcat and Bulldozer

[informal]

2 mem ops per core per cycle
not 3 mem ops(2 load and 1 store) per core per cycle
but .............

Since 10h could do 1x128bit load and 1x64bit store,basically 2x load capability of K8,without even using the 3rd AGU(look at AT article,3rd AGU was redundant/unused but kept for other reasons-symmetry of the units),i don't see how AMD couldn't double this with BD. BD will have a full OoO load/store capability,different what K8->10h brought(limited to loads only). There are other clues about 2 load/1 store per core,namely GCC source code that describes BD scheduling.