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Thread: AMD's Bobcat and Bulldozer

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  1. 08-24-2010, 07:47 PM #10
    vietthanhpro
    vietthanhpro is offline
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    Quote Originally Posted by JF-AMD View Post
    Today's processors have 3 execution units that are shared between ALU/AGU. That is essentially 1.5 ALU and 1.5 AGU. With BD we get 2 AGU and 2 ALU. Much better.
    2 mem ops per core per cycle
    not 3 mem ops(2 load and 1 store) per core per cycle
    but .............
    -------------------------------------
    FPU with
    2x128 bit MMX
    2x128 bit FMAC
    --> non SSE: 4 DP per cycle ?
    --> SSE 128 bit: 8 DP per cycle ?
    --> SSE 256 bit: 8 DP per cycle ?
    Last edited by vietthanhpro; 08-24-2010 at 07:59 PM.
    When AMD had 64-bit and Intel had only 32-bit, they tried to tell the world there was no need for 64-bit. Until they got 64-bit.
    When AMD had IMC and Intel had FSB, they told the world "there is plenty of life left in the FSB" (actual quote, and yes, they had *math* to show it had more bandwidth). Until they got an IMC.
    When AMD had dual core and Intel had single core, they told the world that consumers don't need multi core. Until they got dual core.
    When intel was using MCM, they said it was a better solution than native dies. Until they got native dies. (To be fair, we knocked *unconnected* MCM, and still do, we never knocked MCM as a technology, so hold your flames.)
    by John Fruehe
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