AMD's Bobcat and Bulldozer

[Rise]

Module divisions are transparent... so does that mean natural multi-threading? meaning a single threaded app will be split among 2 cores at the module level?

[Hornet331]

AT covered the issue with the "issue" in their article here. Basically BD will have higher single thread performance than Deneb class cores.

Yes i already read the artciel...

The 3rd ALU does have some performance benefits, and AMD canned it to reduce die size, but AMD mentioned that the 4-wide front end, fusion and other enhancements more than make up for this reduction. In other words, while there’s fewer single thread integer execution resources in Bulldozer than Phenom II, single threaded integer performance should still be higher.

The improtant part is other enhancements.

4way wide frontend is wide, but alone its useless if you can't process the ops fast enough, so the solution is higher clocks speeds aka turbo.

Again i said, its highly likely that bulldozer will have higher singlethreaded performance, but IPC will go down compared to a single deneb core.

[Opteron146]

Again i said, its highly likely that bulldozer will have higher singlethreaded performance, but IPC will go down compared to a single deneb core.

Not necessarily ... 1 ALU is just a tiny little part of the whole machine.

[Hornet331]

Module divisions are transparent... so does that mean natural multi-threading? meaning a single threaded app will be split among 2 cores at the module level?

Each core is shown as own thread to the os.

[informal]

Yes i already read the artciel...



The improtant part is other enhancements.

4way wide frontend is wide, but alone its useless if you can't process the ops fast enough, so the solution is higher clocks speeds aka turbo.

Again i said, its highly likely that bulldozer will have higher singlethreaded performance, but IPC will go down compared to a single deneb core.

IPC will go down?Are you serious ?
Having more underutilized units is bad.Having less units that are constantly fed and always have something to do(the part you made bold) will make the "IPC",the relative and mostly meaningless number (that is 99% of the time <=2), higher. That's the whole point of this machine.

[Mats]

Nope. No integrated PCIe. That would not allow us to use the same sockets.

That would be G34 and C32, is it AM3 as well?

Sorry, it's an obvious desktop question, but given that old roadmaps says YES, and some sources todays says NO, I just wish you could answer.

[madcho]

IPC will go down?Are you serious ?
Having more underutilized units is bad.Having less units that are constantly fed and always have something to do(the part you made bold) will make the "IPC",the relative and mostly meaningless number (that is 99% of the time <=2), higher. That's the whole point of this machine.

IPC can go down if frequency is upped for same performance.

If they double pumped ALU with a double frequency, that could help to use the 4 wide front end.

let me hope for that

[informal]

IPC can go down if frequency is upped for same performance.

If they double pumped ALU with a double frequency, that could help to use the 4 wide front end.

let me hope for that

I doubt they will double pump the ALUs.The units will just be more utilized,a difference from the units in today's parts which sit idle a lot of time .

That would be G34 and C32, is it AM3 as well?

Sorry, it's an obvious desktop question, but given that old roadmaps says YES, and some sources todays says NO, I just wish you could answer.

I think that the guy answering the question in the teleconference got a bit confused. It is possible that the new parts won't work in old boards (and the old CPUs will work in the new boards),but this has never been the case in the past : just look at the AM2/AM2+/AM3 comparison.

[ajaidev]

That would be G34 and C32, is it AM3 as well?

Sorry, it's an obvious desktop question, but given that old roadmaps says YES, and some sources todays says NO, I just wish you could answer.

+1

JF-AMD pls answer this if possible...

[Chumbucket843]

I doubt they will double pump the ALUs.The units will just be more utilized,a difference from the units in today's parts which sit idle a lot of time .

what makes you say this?

high utilization of alu's is one of the hardest things to do. i doubt AMD has improved this dramatically, as it would require a drop in efficiency.

[informal]

what makes you say this?

high utilization of alu's is one of the hardest things to do. i doubt AMD has improved this dramatically, as it would require a drop in efficiency.

Read the AT article.It is the hardest thing to do indeed,but the way this machine is built allows it to go a bit further ahead of itself(with all the BP,data speculation,much improved out of order loads and stores capability etc). I guess the more in depth slides from HotCHips will shed more light on this subject later today.

[G.Foyle]

IPC can go down if frequency is upped for same performance.

IPC is maximum theoretical instructions PER CLOCK. It doesn't go up with frequency.

[Dimitriman]

Here is my take on how BD will operate on sockets AM3 and AM3+

Bulldozer CPU = AM3 and AM3+ compatible

BD + AM3 = Dual Channel DDR3 enabled
BD + AM3+ = Quad Channel DD3 enabled

I bet difference is a few extra memory features on socket AM3+, just as previously done with sockets AM2=>AM2+/AM3

[informal]

Hmm somehow I doubt there will be 4 ch. on AM3+ boards.

[Mats]

*Dreaming*

And how is it possible to cram in two extra channels without adding any pins?

[Dimitriman]

well, I'm only speculating that the difference will be as such that you will get extra benefits on AM3+ but won't hinder AM3 compatibility

But its true QC won't be possible. but perhaps enhanced power features like the turbo mode, could be different on either sockets.

[Dresdenboy]

Ontario 2 core + DX 11 GPU die is about 75 sqmm based on analysis of photos of the wafer shown at Computex.

[Mats]

well, I'm only speculating that the difference will be as such that you will get extra benefits on AM3+ but won't hinder AM3 compatibility

Yeah, I wonder how long we have to wait before we get an answer for that.

No matter if AM3+ have many or very few improvements, AMD won't tell us too soon I guess, because they want to sell as many CPUs and chipsets before BD as possible.

The 870/880G/890GX/890FX was launched this spring, and when was the specs revealed? Two or three months before? And that was even with a chipset with very minor updates, especially the NB.
This makes me think that it isn't very likely that we'll see any specs this year.

This socket confusion will get sorted out pretty soon tho.

[Manicdan]

if BD dosnt drop into AM3, it better be due to costing alot and competing very well, then maybe the extra 100-200$ would be worth while/irrelevant.
since i was just going to wait for AM3+ before dropping AM2+ anyway, im not feeling very hurt, but it does kinda suck

[JF-AMD]

Module divisions are transparent... so does that mean natural multi-threading? meaning a single threaded app will be split among 2 cores at the module level?

No. 1 thread, 1 core. Period.

[Behemot]

There was a telephone conference for the press earlier.
However, at situations like this, the presentators keep some more (detailed) information for the real presentation.

The press information is more like a briefing.

If all the web's complied with NDA, they'd have more info now. Those who did so have the new slides

As for the socket compatibility, there is no info about it in the AMD slides and what was said during the conference call does not say as much as the webs, too. So I guess if they don't have another source they just made the informations trying to hit the mark.

I just can't understand how can you talk on 6 pages about infromations based on nothing? Calm down people! It's starting to be impossible to find something important betwen all the crap here. If it will continue this way, people will move to another forums

[-Boris-]

Well the traditional NB had:
FSB Interface, IMC and SB connection.

Now AMD stresses the IMC, so FSB and SB connector are left out.

FSB is now Hypertransport (well at least from the point of view of Multi processing, otherwise it is the Xbar), and the SB connect was back then PCI, nowadays PCIe - seems fine to me.

FSB Interface was in the processor too, otherwise it couldn't communicate with the NB. So HT has nothing to do with a NB.

NB has always been memory controller, the main bus interface has always been present in the processor. K7 had an area called "Bus interface unit".
So I still can't see what part of the NB except the IMC that has been integrated in Phenom.

[Hornet331]

IPC is maximum theoretical instructions PER CLOCK. It doesn't go up with frequency.

He means, that if you have lower ipc, you can compensate it by increasing the clockspeed to get the same performance.

[Manicdan]

No. 1 thread, 1 core. Period.

i think were all interested about the IPC difference between 2 threads per module and 1, not how much turbo can overclock it, but just how a thread by itself will act (it looks like we already know its going to have 2MB of L2 all to itself)

[superrugal]

Fruehe says that AMD will be able to get six-core and eight-core Bulldozer chips in the 30 to 40 watt power range, which is pretty low for a server. "The question is this," says Fruehe. "Is there a need for a more discrete, less-threaded chip for servers?"

John is this true?