Intel plans to deliberately limit Sandy Bridge overclocking

[informal]

Yeah, let's all start talking about AMD.

Yeah,I don't know why GloFo and Llano launch were dragged into this by terrace.

[Chumbucket843]

No it's not... take a look yourself:

If you consider the 1.2mm2 "a considerable amount",then you are correct sir.
The SSE part of the core has changed negligibly .Where is the widened(256bit) SSE logic?How did it fit inside the same die area?

you must have really good eyes if you can see the SSE and AVX units.

it's easier to claim double pumping like you have but do you realize that the logic required to reach those clock speeds would be 50% more and use 3-10x more power? also did you know that RTL code cant even reach those clocks so you have to custom design millions of transistors?

[Drwho?]

Yeah, let's all start talking about AMD.

Amazing! event in a thread with the title like "Intel plans to deliberately limit Sandy Bridge overclocking" ... The tittle is totally BS, but still ...

[informal]

Hmm theres something wrong with that picture, cause it lsts SB with 2mb, yet its either 1.5mb or 2.5mb l3 per core.

Maybe explanation by Hans here:

The total L3 cache is really 8MB but 1/2 MB of each core is reserved for the GPU:

You can see the 5 identical interfaces to the L3 cache ring. The leftmost is the GPU
interface. At the right there is a 6th somewhat different ring interface to the IMU

you must have really good eyes if you can see the SSE and AVX units.

it's easier to claim double pumping like you have but do you realize that the logic required to reach those clock speeds would be 50% more and use 3-10x more power? also did you know that RTL code cant even reach those clocks so you have to custom design millions of transistors?

I just countered your "greatly increased die area" comment with an actual hard data.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.

[-Sweeper_]

Where did you hear the 1.5/2.5MBs figures?

SB quad-core has 6mb of L3, the hexa & octo-core versions have 15mb and 20mb of L3

do your math

[HelixPC]

I guess the similar rumors where floating when Nehalem was about to be released, so lets see something more concrete before worrying.......

yupp.

[informal]

Sweeper,the 6MBs are actually the usable part of the 8MBs,like Hans explained in the link i posted above... Read up.That's why Hornet asked about the 1.5Mbs of cache dedicated to each core.

[terrace215]

Launch =/= shipment

NVIDIA launched GTX480 / GTX470 in March, and shipped in April.

As AMD & Intel use the terms these days "launch" is AFTER "production shipments" NOT before.

For example, both SB and Ontario will have shipments in Q4 and launch in Q1.

[Hornet331]

Where did you hear the 1.5/2.5MBs figures?

Maybe explanation by Hans here:



I just countered your "greatly increased die area" comment.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.

1,5mb figure come form the ES that where posted here.

dualcore with 3mb
http://www.xtremesystems.org/forums/...d.php?t=250145

quadcore with 6mb
http://forum.coolaler.com/showthread.php?t=240578

2,5mb numbers are still rumors, but since the 1,5mb where spot on I guess there is also somewhat true for SB-E.


Btw. drwho if it might be possible can you gives us a hint if there will be 2 or 3 plattforms? Theres is quite a confusion if S2011 really reaches down to the consumer space or if there is a S1356.

[qcmadness]

As AMD & Intel use the terms these days "launch" is AFTER "production shipments" NOT before.

For example, both SB and Ontario will have shipments in Q4 and launch in Q1.

Let's see if you can get SandyBridge or Ontario in Q1.

[informal]

1,5mb figure come form the ES that where posted here.

dualcore with 3mb
http://www.xtremesystems.org/forums/...d.php?t=250145

quadcore with 6mb
http://forum.coolaler.com/showthread.php?t=240578

2,5mb numbers are still rumors, but since the 1,5mb where spot on I guess there is also somewhat true for SB-E.

Half a megabyte per each core's cache block is reserved for a GPU,so QC SB has 6(8)MB and SB-E has 15MB of usable cache(or following the previous math,actually 3x6=18MB of total cache).

[FlanK3r]

20MB L3 cache seems not possible at 32nm and 1356 LGA....
One question tu Bulldozer, i dont know, if 8 cores are 8 bull. modules or only 4 modules???

To SB: exist samples SB for highend oor to time are only 1155 ES?

[Hornet331]

Half a megabyte per each core's cache block is reserved for a GPU,so QC SB has 6(8)MB and SB-E has 15MB of usable cache(or following the previous math,actually 3x6=18MB of total cache).

SB-E has no gpu...

edit: ok that part with the gpu makes sense, so we have 2mb cache for the gpu alone, not bad.

[informal]

Also as Hornet already asked DrWho,I would like to know more about the s2011 and its possible sliding down to consumer space and how will it co-exist with s1356.

SB-E has no gpu...

Oops forgot about that . Why the 2.5MB figure then? For the iGPU models it makes sense ,but for the E part?

[Hans de Vries]

Sweeper,the 6MBs are actually the usable part of the 8MBs,like Hans explained in the link i posted above... Read up.That's why Hornet asked about the 1.5Mbs of cache dedicated to each core.

Yes, This is why you can have a Sandy Bridge with disabled GPU and 8MB L3 cache (2MB per core).

http://www.xtremesystems.org/forums/...10&postcount=1


Regards, Hans

[qcmadness]

20MB L3 cache seems not possible at 32nm and 1356 LGA....
One question tu Bulldozer, i dont know, if 8 cores are 8 bull. modules or only 4 modules???

To SB: exist samples SB for highend oor to time are only 1155 ES?

4 modules

Now should be low-end (2-4 core)

[Solus Corvus]

I just want to know if there will be unlimited overclocking on non-unlocked parts.

[philo-sofa]

This is really quite a strange move by Intel.... Unless the gulf between Sandy Bridge and Bulldozer is insanely huge this kind of BS will move me straight towards AMD. Hopefully this is just overblown FUD as it was with Nehalem.

[Drwho?]

Yes, This is why you can have a Sandy Bridge with disabled GPU and 8MB L3 cache (2MB per core).

http://www.xtremesystems.org/forums/...10&postcount=1


Regards, Hans

This is incorrect assemptions. Can't say more, but this is pure speculation in the wrong direction, Sorry for the bad news. (The size of the cache and the GPU cache needs are not related, good imagination by the way ;-) )
(The other questions answers are under NDA ... sorry)
The good new is that the title of this thread is totally silly and wrong too

This thread was just a Big piece of
Francois

[Hornet331]

(The other questions answers are under NDA ... sorry)

I feard so, but thx anyway.

[zanzabar]

Amazing! event in a thread with the title like "Intel plans to deliberately limit Sandy Bridge overclocking" ... The tittle is totally BS, but still ...

so coming from an intel guy, the SB will OC. and are all of them really having an IGP, dose intel need graphics share numbers that bad

[FlanK3r]

Drwho?: some evidence about this?

[Drwho?]

Drwho?: some evidence about this?

Well, The AMD bullDozer architect wishes that I answer you (Poker Face), this time, it is like conroe, to figure out the real performance of SB, you will have to wait very close to launch, most of what is out there is not having the right tuning, and I really like it this way.

After all, competition is like a Poker game ... playing with all the card on the table never worked ...


You can decide to believe AMD about SandyB ... but you would not use the most realable experts about 32nm ... outch .. sorry, could not resist

Just friendly jokes, ok ... ?

[Movieman]

Well, The AMD bullDozer architect wishes that I answer you (Poker Face), this time, it is like conroe, to figure out the real performance of SB, you will have to wait very close to launch, most of what is out there is not having the right tuning, and I really like it this way.

After all, competition is like a Poker game ... playing with all the card on the table never worked ...


You can decide to believe AMD about SandyB ... but you would not use the most realable experts about 32nm ... outch .. sorry, could not resist

Just friendly jokes, ok ... ?

Francois:
This isn't just to you but to all companies.
ALL of you want to hide the numbers till the day the parts release.
I think your all wrong in your thinking.
IF it's a great part then shout it to the world.
Show it,tout it,say to the world: "Beat this you suns a biatches"
Oh, did I say I'm a sort of in your face type of guy?

[ReverendMaynard]

cheers to that MM lol. Honestly the NDA thing is played out, and with the cloud hanging over the oc community right now, some good bloody news would be awesome