Quote Originally Posted by informal View Post
The total die size mostly depends on the L3 sram cell size and intel (currently) reigns supreme here. Core logic die area in Nehalem is vastly larger than that one in Shanghai,but still Shanghai does not have 60% less performance than comparable Nehalem chip(the advantage varies and is between 20 to 25% ,on average,depending on the workload selection). Nehalem does have 3ch. IMC which is clearly advantage for server workloads.AMD dealt with this advantage when they transitioned to Opteron 6000 series.
I can find you dozens of industry standard benchmarks where Nehalem has close to 2x if not more the core performance of a Shanghai core. And in the end, that's what really matters. Purchase decisions are based on that, not on games. Good luck with corporate buyers selling them game performance.


Quote Originally Posted by Manicdan View Post
how is core size not relevant? the process of the cache is vastly different and very space consuming for AMD. if they used the same method Intel did would you still be able to use "theyre the same size" argument?

All that matters is die size. That translates into $. You save some mm^2 on the core and lose on cache or the other way around, it doesn't matter if the end results are similar and one performs much better than the other.

Please explain what you mean by this, because in the end, it not only takes more space, but is slower.