Quote Originally Posted by JumpingJack View Post
My guess is that it is going to 5 issue and that they will widen the execution window, this will have two main effects -- single threaded performance (IPC) will see a nice pop (say 10% or so, not more than 15% I suspect), but HT situations will see a real improvement with a wider core, so heavy multithreading may show even better gains.
The frond-end wasn't changed much as i know (with the exception of larger Loop detect buffer - can we call it trace cache now?). A back-end logic in Nehalem already can issue 6 uops each cycle (to 6 execution ports). In SB a load instruction can be issued on port 3 (in addition to port 2) that is up to 2 load uops can be issued each cycle (in Nehalem load uops can be issued on port 2 only).