This particular example is of course an ideal case for 256 bit hardware
and now Sandy Bridge's 48 byte/cycle versus Llano's 32 byte/cycle
L1 cache bandwidth will determine the throughput.
Regards, Hans
Well, it looks like 32 byte/cycle is enough to keep up (assuming we need 1 (or 2, for the 128-bit hardware) cycle to accumulate the new 256 bit value into the running sum anyhow), so wouldn't it be roughly 2:1 in this case?
Last edited by terrace215; 04-22-2010 at 06:42 PM.
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