Dresdenboys' blog: AMD Bulldozer - Patent based research part 2

[Chumbucket843]

I don't have the DDR-3 platform right now, but if you use Everest Memory test, you can get about 10GB/s for L3 cache on Deneb.



It would be the design of the L3 / IMC.

In K8 architecture, IMC directly communicates with L2 cache in each core.
The simple illustration is the CnQ-throttled CPUs have lower memory speed.

In K10 architecture, IMC communicates with L3 cache (or NB?) and the bandwidth is limited to NB frequency.

http://www.xbitlabs.com/articles/cpu...0_8.html#sect4
it never touches the memory controller, its been that way for like 15 years! iirc dual independent buses were on pentium 2. a memory controller is basically like a server/client network that is used for DRAM only. it runs at the same frequency as the DRAM clockspeed. the whole idea of L3 cache is so cores can communicate with out touching mem controller or main memory. as far as bandwidth goes it should be around 50GB/s with significantly lower latency.

[qcmadness]

http://www.xbitlabs.com/articles/cpu...0_8.html#sect4
it never touches the memory controller, its been that way for like 15 years! iirc dual independent buses were on pentium 2. a memory controller is basically like a server/client network that is used for DRAM only. it runs at the same frequency as the DRAM clockspeed. the whole idea of L3 cache is so cores can communicate with out touching mem controller or main memory. as far as bandwidth goes it should be around 50GB/s with significantly lower latency.

but then it could not explain the lower DDR-2 memory bandwidth when comparing K10 with K8?

[informal]

but then it could not explain the lower DDR-2 memory bandwidth when comparing K10 with K8?

I think it's the problem of measuring the BW on 10h systems due to design change(unganged/ganged is a new thing in 10h Vs the old K8). I remember very well that first sisoft sandra results very very poor on 10h simply because the app was not programmed for the new IMC organization 10h had when it showed up.
What matters is memory latency and L3 helps a lot(as any cache does since it is heaps faster than any regular DDR memory out there).
Now BD will have much improved memory controller and will support even higher DDR3 speeds (1600+). That should be enough even for 8 cores.

[Chumbucket843]

but then it could not explain the lower DDR-2 memory bandwidth when comparing K10 with K8?

that could be a number of things. informal mentioned the memory controller which is a likely cause.