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Thread: Dresdenboys' blog: AMD Bulldozer - Patent based research

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04-19-2010, 04:46 AM #16
vietthanhpro

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Originally Posted by Hans de Vries

Originally Posted by TacoBell

Originally Posted by yfe

Originally Posted by jack

Yes. K10 core has 3 integer ALUs, while Bulldozer "cluster" has 2 integer ALUs (Bulldozer core has 4 integer ALUs in total).

Where did you get it from? Don't you mix it with Bobcat?
On Bulldozer pic, four pipelines/core are shown only, w/o any details.

Ars claims 4 pipes = 2 ALU + load + store

The patents do show this and it corresponds with AMD's Bobcat diagram.
Bulldozer's diagram however shows 4 integer ALU's and no load & store.

This indicates the load and store address calculations are probably
done by the ALU's. (It already a while that the 3 operand adds aren't
used anymore in the address calculation)

Regards, Hans

link:http://aceshardware.freeforums.org/p...57.html#p12357

When AMD had 64-bit and Intel had only 32-bit, they tried to tell the world there was no need for 64-bit. Until they got 64-bit.
When AMD had IMC and Intel had FSB, they told the world "there is plenty of life left in the FSB" (actual quote, and yes, they had *math* to show it had more bandwidth). Until they got an IMC.
When AMD had dual core and Intel had single core, they told the world that consumers don't need multi core. Until they got dual core.
When intel was using MCM, they said it was a better solution than native dies. Until they got native dies. (To be fair, we knocked *unconnected* MCM, and still do, we never knocked MCM as a technology, so hold your flames.)

by John Fruehe