I've spent quite some time reading through the whole thread I started playing around with my OC again.
I would like to share my settings as well as ask A-Grey Mikeyame greg.m especially for some suggestions to improve on the result.
CPU: E8500 C0 SLAPK Q817A608 (D-Tek FuZion v2)
MOBO: ASUS Rampage Forumla rev. 1.03G made in China BIOS v0902 (MOSFETS NB & SB Watercooled)
RAM: G.Skill F2-9600CL5D-4GBPI CL5-5-5-15 2.1v (active aircooled)
*Extreme Tweaker*
Ai Overclock Tuner [Manual]
CPU Ratio Setting [09.5]
FSB Strap to North Bridge [Auto]
FSB Frequency [455]
PCIE Frequency [110]
DRAM Frequency [DDR2-1213MHz]
DRAM Command Rate [Auto]
DRAM CMD Skew on Channal A [Greyed Out]
DRAM CMD Skew on Channal B [Greyed Out]
DRAM CLK Skew on Channal A [Auto]
DRAM CLK Skew on Channal B [Auto]
DRAM Timing Control [Auto]
1st Information
CAS# Latency [5]
RAS# to CAS# Delay [5]
RAS# PRE Time [5]
RAS# ACT Time [15]
RAS# to RAS# Delay [3]
REF Cycle Time [52]
WRITE Recovery Time [6]
READ to PRE Time [3]
2nd Information
READ to WRITE Delay (S/D) [8]
WRITE to READ Delay (S) [3]
WRITE to READ Delay (D) [5]
READ to READ Delay (S) [4]
READ to READ Delay (D) [6]
WRITE to WRITE Delay (S) [4]
WRITE to WRITE Dealy (D) [6]
3rd Information
WRITE to PRE Delay [14]
READ to PRE Delay [5]
PRE to PRE Delay [1]
ALL PRE to ACT Delay [6]
ALL PRE to REF Delay [6]
DRAM Static Read Control [Disabled]
Ai Clock Twister [STRONG]
Ai Transation Booster [Manual]
Common Performance Booster [6]
Pull-In of CHA PH1 [Disabled]
Pull-In of CHA PH2 [Disabled]
Pull-In of CHA PH3 [Disabled]
Pull-In of CHA PH6 [Disabled]
Pull-In of CHB PH1 [Disabled]
Pull-In of CHB PH2 [Disabled]
Pull-In of CHB PH3 [Disabled]
CPU Voltage [1.4870] REAL [1.480]
CPU PLL Voltage [1.54] REAL [1.616]
North Bridge Voltage [1.69] REAL [1.712]
DRAM Voltage [2.04] REAL [2.096]
FSB Termination Voltage [1.50] REAL [1.424]
South Bridge Voltage [1.100] REAL [1.120]
SB 1,5V Voltage [1.55] REAL [1.584]
Loadline Calibration [Enabled]
CPU GTL Voltage Reference [0.63x]
NB GTL Voltage Reference [0.67x]
DRAM Controller Voltage REF [DDR_REF] REAL [1.040]
DRAM Channel A Voltage REF [AUTO]
DRAM Channel B Voltage REF [AUTO]
CPU LED Selection [CPU Voltage]
NB LED Selection [North Bridge Voltage]
SB LED Selection [South Bridge Voltage]
Voltiminder LED [ENABLED]
CPU Spread Spectrum [Disabled]
PCIE Spred Spectrum [Disabled]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [Normal]
These are the min settings I could run stable using IBT. I tried every possible GTL combination with no success.
I've tried 460FSB with high volts upto:
CPU Voltage REAL [1.560]
CPU PLL Voltage REAL [1.712]
North Bridge Voltage REAL [1.744]
with no success

Is there a known ratio of vCore PLL FSBT & vNB which needs to be applied?
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