I'm obviously talking about the CUDA API, not about the CUDA architecture. The CUDA architecture is something internal, as it's the ISA, and access is granted through other intermediate layers, so nothing to standardize here. It's their propietary API what they want to see used, nobody uses "architectures" directly...
That's exactly the problem, IMO (and it's extensible to the previous gen too).
NVIDIA is trying to reach a new (emerging) market, what they call the HPC market, with their architecture. The problem is that this new market isn't there yet, so they can't split their R+D and chip manufacturing in 2 different architectures and/or product lines, so they have to make 3D rendering chips (the current market) that are good for the HPC market.
That eats transistors, developement of the architecture, and so. So the resultant chip isn't specialiced to the 3D rendering market, and has difficulties to compete with other products that are (in an efficiency performance/features to cost manner).
I'm starting to think that's the main reason of the weak performance to size ratio of the past generation, and I'm starting to think that we are going to see a repeat in this one.




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