Quote Originally Posted by Dresdenboy View Post
I didn't say 8 threads (just 2), but I wrote about the micro ops. So this means that one thread could have one (probably even more) microcoded (complex) operations decoded, while the other thread could be decoded using the fast path decoders. So one thread with simple ops could be decoded for the appropriate int cluster while the second thread could have some (probably microcoded, see the KGC blog entry) AVX instructions being decoded for the FPU.
Given that all previous CPUs indicate that Microcoded operations are rare, the excessive transistors dedicated to a single thread would be wasteful.
fast path decoding is more energy efficient, and cheaper in transistor counts.
Thus the logical outcome is that if there are 8 decoders, is that at most only 2 of them would be micro-decoders and the remaining 6 should be fast path.