Quote Originally Posted by Dresdenboy View Post
I didn't say 8 threads (just 2), but I wrote about the micro ops. So this means that one thread could have one (probably even more) microcoded (complex) operations decoded, while the other thread could be decoded using the fast path decoders. So one thread with simple ops could be decoded for the appropriate int cluster while the second thread could have some (probably microcoded, see the KGC blog entry) AVX instructions being decoded for the FPU.
Thank you very much. I needed that clarification. Will taking advantage of that capability require specific software enhancements for this architecture or does this look like a method the CPU can handle with any basic software coded with AVX support? As you can tell, I'm no expert by any means, but I want to just have an idea whether or not software engineers have to do AMD specific coding to get these enhancements to work or not (like SSE4A).