Madhsrimps artricle about tRD (performance level) on i7!

[The-Fox]

Thanks for the info and support Felix, you are truly a Gem to our community, what would we do without you ?

I am quoting from Intel's datasheet Felix has linked:

B2B_CAS_DELAY.
Controls the delay between CAS commands in DCLKS. The minimum spacing is
4 DCLKS. Values below 3 have no effect. A value of 0 disables the logic. Setting
the value between 3-31 also spaces the read data by 0-29 DCLKS. The value
entered is one less than the spacing required, i.e. a spacing of 5 DCLKS
between CAS commands (or 1 DCLK on the read data) requires a setting of 4.

So, massman, do you want to confirm that 0-3 values has not effect ? :p