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RTL is more tRD than anything else on this platform, the RTL value is a result of the post Tx equation and sets the read back time from the DIMM's (the the IMC needs to be ready within that window for the transfer to take place). All downstream offsets between the Uncore an CPU are set according to RTL. CAS perforamance can be mirrored by adjusting the RTL value by upto 4ns past the sensed value, so long as a transistor pad is avaialble by the time of a readback request you'll get a post. In effect one can get CAS 8 performacne at CAS 7 if the value is moved out too far. Basicaly speaking keep RTL as tight as possible if you want the fastest performance at every point. The only thing I have not looked at much is the effect of higher Uncore frequencies upon the avaialable RTL window.
Last edited by Raja@ASUS; 07-07-2009 at 08:36 AM.
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