By looks of it hus bandwidth is cripped slightly from adding extra Advance on DRAM delay skews to pull off PL6 without too much extra Vnb and keep the thing stable. That's my take on it anyhow.
A-Grey,
Not bad mate, good to see you took those clown shoes off and got the thing working a bit better
By the way the CPU/NB clock skew delay increment is limited by the resolution achieved through MCHBAR register adjustment which as you imagine is what Intel designed into the MCH. I've never seen a bios use anything but 100ps steps on X48/P45, all vendors alike. This pretty much confirms it is achieved through MCHBAR registers since not all vendors use same clock generator.
Now I don't have the faintest idea where you will find the value, but I have a rough idea. It'll be somewhere between either 000-100h or B00-FFFh. First range looks like it holds initialization values, and the second range contains registers which are used for clock driving/receiving/compensation and GTL+ circuit adjustment, such as MCH slew rate, MCH vref adjustment, GTL buffer strength, Host slew Rate input, etc. So if anything it should be in here.
Basically Asus are stuck with the same adjustment steps that everybody else is. Intel obviously didn't go any higher with resolution because cost to manufacture would go through the roof, and I don't think they'd be able to just say well we gave the overclockers higher resolution clock skew adjustment, so all your chips are now worth $50 more to purchase. They'd have stock that'd never sell

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