AMD embraces AVX making a new superset with SSE5(256bit support)

[Donnie27]

Why not just get the updated info from Intel?

http://software.intel.com/en-us/avx/

Intel® AVX (Intel® Advanced Vector Extensions) is a 256 bit instruction set extension to SSE and is designed for applications that are floating point intensive.

Let's see, as the architecture improves, shouldn't Intel update AVX accordingly? If that causes AMD heartburn then, that means they have to work harder. Or should Intel not do improvements to help AMD? Intel has always improved SIMD's and hell, I hope they continue to.

http://software.intel.com/en-us/foru...s/topic/61121/

I have heard that Sandy Bridge won't have FMA implementation.

If that rumor is true, I would really like to know who decided that x86 developers should wait more to finally get fused multiply-add isntruction? Is it so useless in real code or the marketing department has again started doing an engineer's job?

Hereby I publicly voice my displeasure over that poor decision.

Hi Igor,

Sandy Bridge will not have FMA, it's targeted for a future processor. I apologize if there is any confusion I (or Intel) caused. In our defense, we did discuss feature timing in the last two Intel developer forums (and now to my embarrassment, I see that presentation has been removed from the IDF content catalog at http://www.intel.com/idf , we'll have it up in time for the upcoming IDF on Oct 20). And it's on a separate CPUID feature flag (separate section of the document too ) in the programming reference.

Yes, it changed alright ajaidev