AMD embraces AVX making a new superset with SSE5(256bit support)

[Mechromancer]

^Actually, SSE5's outline was released 8 months before Intel's AVX and Intel seemingly implemented quite a bit of SSE5.

[informal]

Even if you have it, you go there and lost 1 entire day comparing 100++ instructions 1 by 1? Ya right

Shintai is bsing again.AMD has no reason to post AVX spec since its intel's specification and its on intel's site.AMD clearly said,in no uncertain terms, they will support AVX version 5 and FMA version 3 in BD cores.It can't be any clearer.What this means is that instruction format must be equivalent between SB and BD in order to run the AVX optimized code written for SB on BD or the other way around. Both specs,for AVX nad FMA are available on intel's webpage covering AVX.
What SB won't have is any form of FMA(this is current official stance at intel).SB will have "basic" AVX ,with new media instructions and wider vector support.By the time intel gets to implement FMA at all,AMD's FMA4 approach (which is superior without a doubt) will be on the market for some time already and will probably make intel adopt it or make their own similar(to AMD's) 4 operand fused multiply add format.

^Actually, SSE5's outline was released 8 months before Intel's AVX and Intel seemingly implemented quite a bit of SSE5.

Yes,but AMD played it safe this time and now will support both AVX and it's own XOP,CVT16,FMA4 extensions in one set(call it AVX2 if you like).The XOP etc. additional set is a "remnant of SSE5",the instructions that were not covered by AVX are still implemented as a bonus set(a la 3Dnow,lets hope they will get used this time around). This means a lot for software developers who will have a much easier time coding for common instruction set instead of optimizing for different ones-both devs and consumers will benefit from this. They can also optimize for FMA4 and XOp since BD will offer these too,a clear advantage for AMD.

[Brother Esau]

i have nothing more to say after your last post to that.

@ topic

its nice to see amd get FMA before intel and i also hope this time the have some big compiler devs behind them (or even better release there own compilers) to make use of this instructions.

Why should you? You are nothing But a Deceitful Flame Baiter and you already have my attention and response Just remember to send Me And everyone else that Debugged Phenom Quad Core IMC a Christmas Card for Giving you the Info that you needed not to Blow Up your New Toy

Gotta Love it when the Shoe is on the other Foot and you all get to Eat your own words1


B.T.W......Is It Smooother?????

[Hornet331]

Why should you? You are nothing But a Deceitful Flame Baiter and you already have my attention and response Just remember to send Me And everyone else that Debugged Phenom Quad Core IMC a Christmas Card for Giving you the Info that you needed not to Blow Up your New Toy

Gotta Love it when the Shoe is on the other Foot and you all get to Eat your own words1


B.T.W......Is It Smooother?????

this makes absolute no sense at all... can someone translate this for me?
btw. i wonder woh is flamebaiting the whole time...

[Brother Esau]

this makes absolute no sense at all... can someone translate this for me?
btw. i wonder woh is flamebaiting the whole time...

Translation = Smoother

[Brother Esau]

this makes absolute no sense at all... can someone translate this for me?
btw. i wonder woh is flamebaiting the whole time...

Well now you know damn well I do not come into any thread and flame bait anyone

So how does it Feel to get a taste of your own medicine , not particually Fun now is it?


Make a Note: to yourself to start being a nicer person!

[[XC] riptide]

Everybody. Be cool.

[informal]

More information on AVX support in BD cores,directly from senior architect Mr. Christie,as response to Agner Fog's inquiry in comments section of the blog:

AMD deserves praise for this important move towards convergence and compatibility. The changes in the SSE5 spec. have very much followed the lines I have argued heavily for in the AMD developer forum and elsewhere. It is impossible to maintain compatibility when the development cycle is several years and AMD and Intel both keep secrets to each other. It was therefore a very good move when AMD published their proposed SSE5 spec years in advance. A move that Intel responded to by also publishing their AVX proposal in advance. Let's hope this new tradition continues. The whole industry is crying for compatibility. I can certainly imagine your reaction when Intel announced their last minute change from FMA4 to FMA3!

Our worst nightmare would be Intel copying the XOP instructions but making them incompatible with AMD by replacing the XOP prefix by a VEX prefix. I hope you have legal remedies to prevent such a move.

Could you perhaps outline a roadmap for if or when the various instruction sets will be supported by AMD CPUs:

* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers

How much of this will be supported in Bulldozer?

Agner Fog's post at Ace's:

According to Dave Christie, AMD will support all Intel instructions in Bulldozer, including AVX, SSE4.1-2, AES and PCLMULQDQ.
http://forums.amd.com/devblog/blogpo...d=208#comments.

They must have been working very hard to implement all that within such a short timeschedule. I am sure they will implement the 256-bit vector registers as two 128-bit registers, but so will Intel.

So another confirmation of the topic title and another proof shintai was wrong

[Chad Boga]

More information on AVX support in BD cores,directly from senior architect Mr. Christie,as response to Agner Fog's inquiry in comments section of the blog:


Agner Fog's post at Ace's:


So another confirmation of the topic title and another proof shintai was wrong

So doesn't AMD supporting all the AVX instructions make a mockery of your claims that Intel was purposely introducing incompatibilities to f@@k up AMD?

[informal]

So doesn't AMD supporting all the AVX instructions make a mockery of your claims that Intel was purposely introducing incompatibilities to f@@k up AMD?

No,read up before posting nonsense. Intel changed the FMA format, which is not an integral part of AVX.Intel plans to add FMA only at later point,after Sandy Bridge.They change it at last minute thus rendering AMD's early implementation incompatible with their new format.AMD will use more powerful FMA4 in BD cores,instead of FMA3 in Ivy Bridge.

Better luck next time though

PS all can see shintai is now avoiding this thread like a plague ,circling around it hoping the thread will go away and his pwng is forgotten .He's "pulling a sh..." on us

[Hornet331]

No,read up before posting nonsense. Intel changed the FMA format, which is not an integral part of AVX.Intel plans to add FMA only at later point,after Sandy Bridge.They change it at last minute thus rendering AMD's early implementation incompatible with their new format.AMD will use more powerful FMA4 in BD cores,instead of FMA3 in Ivy Bridge.

Better luck next time though

PS all can see shintai is now avoiding this thread like a plague ,circling around it hoping the thread will go away and his pwng is forgotten .He's "pulling a sh..." on us

the last sentence was unneccassary:
http://www.xtremesystems.org/forums/...6&postcount=16

[informal]

the last sentence was unneccassary:
http://www.xtremesystems.org/forums/...6&postcount=16

So was the last sentence here:

And Phenom was 50% faster than Core 2 also..ye...

So in short, you cant. Because you dont know. You claim its a superset. Yet you dont know.

AMD expects to support a partial portion of AVX. What AMD calls AVX is funny enough not the same as what Intel calls AVX. Plus inside AVX you also got FMA, VEX.128, VEX.256 and AVX.

There was a reason i called you a marketing tool.

He never bothered to admit he was plain wrong.He kept putting me down over and over again and when proved wrong over and over again he keeps silent and plays dumb now.

[Lightman]

It really is good news for everyone!
Executables will not get unnecessary bigger, programmers will have less to worry about and they will have more resources to properly optimize they code-path and new programmers will have less to learn about.

I'm glad AMD did that move, I just hope at some point both parties will agree on direction which to take for future ISA extensions.

[Eson]

The day Shintai admit he is wrong is the day when the world ends.

[Tomasis]

informal, well done

Now better that intel doesnt mess up again.

[informal]

The day Shintai admit he is wrong is the day when the world ends.

Or hell freezes over

informal, well done

Now better that intel doesnt mess up again.

Thanks . At first there was a lot of confusion around what is supported and what is not,so things are much clearer now

[Katzenschleuder]

Its SSE5 thats AMDs own invention. In short its another 3DNow!, SSE4A. Good luck!

AVX and SSE5 is fully incompatible so to say.

Nothing new really, nothing surprising.

http://en.wikipedia.org/wiki/Advanced_Vector_Extensions
http://softwarecommunity.intel.com/i...e-31943302.pdf
http://en.wikipedia.org/wiki/SSE5

SSE5 is more a SSE4 competitor than AVX.

One shouldn't judge about something without having a clue about the matter!

[informal]

Haha,that was really funny^^

[Hans de Vries]

More information on AVX support in BD cores,directly from senior architect Mr. Christie,as response to Agner Fog's inquiry in comments section of the blog.

According to Dave Christie, AMD will support all Intel instructions in Bulldozer, including AVX, SSE4.1-2, AES and PCLMULQDQ.
http://forums.amd.com/devblog/blogpo...d=208#comments.
Agner Fog's post at Ace's

So, everthing fine, everthing ok, so far for compatibility.
It takes an astounding endurance and resilience to get the message through though.

It might well be that it's not true that Intel changed the FMA stuff just to make things hard for AMD.
They had no real obligation to publish AVX that early anyway. It's more likely simply an implementation issue.


Regards, Hans

[Zucker2k]

Shintai is bsing again.AMD has no reason to post AVX spec since its intel's specification and its on intel's site.AMD clearly said,in no uncertain terms, they will support AVX version 5 and FMA version 3 in BD cores.It can't be any clearer.What this means is that instruction format must be equivalent between SB and BD in order to run the AVX optimized code written for SB on BD or the other way around.

How are you guys reading this thread? Stop patting yourselfs on that back already; I have bolded some significant parts of that post to give the undiscerning an idea about how the real intentions of AMD have been subtletly presented by informal. It's simple, AMD's plan in this is to assume the equal of Intel and Intel is clearly not interested in making that happen. shintai said that clearly in the beginning and some chose to avoid that, but it all boils down to who is the industry leader and how they choose to introduce technology into the market. It's interesting to say the least, that some AMD fans would pretend they know what Intel's plans are. Besides, if BD supports FMA3 then what's the hue and cry about? From a business standpoint, Intel has every right (and have earned it) to call the shots. I think while it'll be good to see some collaboration between the chip makers, AMD's approach is a little too aggressive since they're not the leading player in the market and nobody is going to implement code that Intel doesn't adopt. So what's the jubilation about?

Also, informal you need to read your own posts sometimes, because you used words like "stupid" and "dumb" and I'm sure it makes you feel good - but it blows my mind that you'll reproach somebody else for doing same.

[v_rr]

You sure talk alot. But you cant list anything? Where is the pdf etc with AMDs instructionlist?

Have a nice day:
AMD64 Architecture
Programmer’s Manual
Volume 6:
128-Bit and 256-Bit
XOP, FMA4 and CVT16
Instructions
http://support.amd.com/us/Processor_TechDocs/43479.pdf

[Shintai]

Have a nice day:
AMD64 Architecture
Programmer’s Manual
Volume 6:
128-Bit and 256-Bit
XOP, FMA4 and CVT16
Instructions
http://support.amd.com/us/Processor_TechDocs/43479.pdf

So none of the VEX.128 and VEX.256 promoted instructions listed in table A.1 of the Intel AVX spec. And not a full support of the AVX, FMA and AES instructions in A.2

OUCH!!!! Superset and full support my rear end.

Unless this radically changes. Then AMD only got partial AVX support.

[informal]

Oh my God. Shintel you really have some issues. The list is for the new additional instructions(made by AMD,in-house from previous SSE5 spec and addopted to VEX decoding) ,apart from AVX support.This is emphasized by Mr. Christie.AMD will support AVX version 5 and FMA version 3(FMA4) AND additionally add their own XOP extensions vrr linked to. AVX is already listed on intel's site(both of versions AMD mentions) and these are intel's extensions.
Man,you are really full of surprises lol
Such a simple concept and you still don't get it. Look up the :superset. Also look up words: full,support, and combination of these.

[Shintai]

Oh my God. Shintel you really have some issues. The list is for the new additional instructions(made by AMD,in-house from previous SSE5 spec and addopted to VEX decoding) ,apart from AVX support.This is emphasized by Mr. Christie.AMD will support AVX version 5 and FMA version 3(FMA4) AND additionally add their own XOP extensions vrr linked to.

Man,you are really full of surprises lol

If you can list the additional instructions i will be happy to eat my words. Until then its up to you to prove otherwise.

But I doubt you can, since this is Volume 6. Hence there is NO former SSE5 instructions.

Volume 1: Application Programming 24592
Volume 2: System Programming 24593
Volume 3: General-Purpose and System Instructions 24594
Volume 4: 128-Bit Media Instructions 26568
Volume 5: 64-Bit Media and x87 Floating-Point Instructions 26569
Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions 43479

Or do we need to wait for volume...7?

[informal]

I already linked to one of the designers of very Bulldozer core. You can start eating ... now. Maybe you are a secret member of Bulldzoer design team ? If you are,then you probably know better than Mr. Christie lol

Also a re-post of my previous post :

More information on AVX support in BD cores,directly from senior architect Mr. Christie,as response to Agner Fog's inquiry in comments section of the blog:

AMD deserves praise for this important move towards convergence and compatibility. The changes in the SSE5 spec. have very much followed the lines I have argued heavily for in the AMD developer forum and elsewhere. It is impossible to maintain compatibility when the development cycle is several years and AMD and Intel both keep secrets to each other. It was therefore a very good move when AMD published their proposed SSE5 spec years in advance. A move that Intel responded to by also publishing their AVX proposal in advance. Let's hope this new tradition continues. The whole industry is crying for compatibility. I can certainly imagine your reaction when Intel announced their last minute change from FMA4 to FMA3!

Our worst nightmare would be Intel copying the XOP instructions but making them incompatible with AMD by replacing the XOP prefix by a VEX prefix. I hope you have legal remedies to prevent such a move.

Could you perhaps outline a roadmap for if or when the various instruction sets will be supported by AMD CPUs:

* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers

How much of this will be supported in Bulldozer?

Agner Fog's post at Ace's:

According to Dave Christie, AMD will support all Intel instructions in Bulldozer, including AVX, SSE4.1-2, AES and PCLMULQDQ.
http://forums.amd.com/devblog/blogpo...d=208#comments.

They must have been working very hard to implement all that within such a short timeschedule. I am sure they will implement the 256-bit vector registers as two 128-bit registers, but so will Intel.

So another confirmation of the topic title and another proof shintai was wrong


* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers

I should have mentioned something about these. We intend to support all of it, with the possible exception of CVT16, which might not appear in the initial AVX-compatible products (hence the separate feature flag)