X48 Rampage Formula Preview.

[RCG_Bex]

I know, but I got this QX real cheap and it's now lapped. I've ran 4.4ghz stable before, its just trying to get that combo again...

Increased the NB to 1.45v and VTT to 1.36, ran for ~3hrs then stops responding again. Upped NB voltage again but if anything, its worse >.<

On my old RAM my board wasn't fussy, but this RAM seems to cause problems if my board is overvolted somewhere

~Bex

[Fritz_the_germ]

Hi folks!
I got my new G.Skills 2*2 Gig PC-9600 a few hours ago. They ran one hour trough memtset 2.11, test 5#, passed 33 loops without any errors.
Each time I call up to my vista 64 partition, I get freeze. On vista runs memset4, that forces the 16,383 tREFs.
The W 7 partition runs pretty good without memset. I have 3120T tREFs though.
Here are my bios settings:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [450]
FSB Strap to North Bridge [400]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1,200MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [6]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1,30625V]
CPU PLL Voltage [1,54V]
North Bridge Voltage [1,33V=1,36V real]
DRAM Voltage [1.96V=2,04V real]
FSB Termination Voltage [1,24V=1,16Vreal]
South Bridge Voltage [1,05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

Is my vDIMM correct?
The tag on the sticks says "stock voltage 2.1v".
Alien Grey told me a few posts before that he was running them on 1,200 Mhz with ~1.8 volts.
Should I set "Auto" on DRAM Skew on Channel A or B instead of 100 ps because Everest tells me 10T Clock Fine Delay on all 4 (?) Dimms even when I have just 2 sticks?
The lower the number of the Clock fine delay timings the better runs my system, doesn´t it?

[mikeyakame]

Hi folks!
I got my new G.Skills 2*2 Gig PC-9600 a few hours ago. They ran one hour trough memtset 2.11, test 5#, passed 33 loops without any errors.
Each time I call up to my vista 64 partition, I get freeze. On vista runs memset4, that forces the 16,383 tREFs.
The W 7 partition runs pretty good without memset. I have 3120T tREFs though.
Here are my bios settings:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [450]
FSB Strap to North Bridge [400]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1,200MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [6]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1,30625V]
CPU PLL Voltage [1,54V]
North Bridge Voltage [1,33V=1,36V real]
DRAM Voltage [1.96V=2,04V real]
FSB Termination Voltage [1,24V=1,16Vreal]
South Bridge Voltage [1,05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

Is my vDIMM correct?
The tag on the sticks says "stock voltage 2.1v".
Alien Grey told me a few posts before that he was running them on 1,200 Mhz with ~1.8 volts.
Should I set "Auto" on DRAM Skew on Channel A or B instead of 100 ps because Everest tells me 10T Clock Fine Delay on all 4 (?) Dimms even when I have just 2 sticks?
The lower the number of the Clock fine delay timings the better runs my system, doesn´t is?

With those Fine Clock Delay values they are autodetected, and when dimm slots are empty their autodetect value is generally calculated as turn around for reply timeout.

Dimm 1 / 2 = A1 / A2, Dimm 3 / 4 = B1 / B2,

With 2GB sticks you don't want generally more than 5 or 6T in the dimm slots you have filled, 3T - 5T when you go above 470mhz fsb.

I've yet to come to a solid understanding on what the hell the number means, but you can assume that generally 1T will probably equal somewhere in the range of 70-90ps.

With Dimm2/4 occupied on my DFI board as an example.

Autodetect on Dimm1, 480ps delay on Dimm2, Autodetect on Dimm3 and 510ps delay on Dimm 4 gives me 9T/6T/10T/6T

What Asus does with Dram Clock Delay Skew is takes the autodetect value calculated initially when sampling flight time delay from driving the clock/control/command at host bus until a response is issued at the receiving end on each memory slot.

Delay increments are added to the calculated flight time delay, or Advance increments are subtracted from the calculated flight time delay. What Asus never bothered to do is correctly implement them in a meaning manner.

1T = whatever the base step degree value is necessary to give the calculated delay skew value at any one point in time. If MCH calculates 300ps dimm1, 360ps dimm2, 395ps dimm3, 455ps dimm4, then base step degree will be whatever the closest step selection is available which can be used for channel a clock fine delays for example. Step might be 90ps in this example as all 4 dimm flight delays will be pretty close to the calculation for x amount of degrees using that base step selection. 90ps @ 4 degrees gives 360ps, 90ps @ 5 degrees gives 450ps, 1T = 1 degree of base step.

[Fritz_the_germ]

Thank you for your reply, mikeyakame.
It´s amazing that I´m correspondending with somebody from the other side of the world. My best greetings to australia!
But back to the dimms.
Please respect that I have to translate and to understand what you told me about the Dram Clock Delay Skew. Before it hits right into my mind could you suggest the probably best pick of the DRAM Clock fine delay for my system regarding my bios settings one post ago?

Would it be possible to set the Ai Clock Twister to strong or even stronger instead of moderate?

[RCG_Bex]

NB @ 1.55v and VTT @ 1.36v for 4Ghz - runs stable, tried 410 and it's started dying again and upping volts isn't going great.... *sigh* I think its maybe time to trade her in - really annoyed though because with the 3870X2 she ran 4.4Ghz!

~Bex

[Alien Grey]

Hi folks!
I got my new G.Skills 2*2 Gig PC-9600 a few hours ago. They ran one hour trough memtset 2.11, test 5#, passed 33 loops without any errors.
Each time I call up to my vista 64 partition, I get freeze. On vista runs memset4, that forces the 16,383 tREFs.
The W 7 partition runs pretty good without memset. I have 3120T tREFs though.
Here are my bios settings:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [450]
FSB Strap to North Bridge [400]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1,200MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [6]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1,30625V]
CPU PLL Voltage [1,54V]
North Bridge Voltage [1,33V=1,36V real]
DRAM Voltage [1.96V=2,04V real]
FSB Termination Voltage [1,24V=1,16Vreal]
South Bridge Voltage [1,05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

Is my vDIMM correct?
The tag on the sticks says "stock voltage 2.1v".
Alien Grey told me a few posts before that he was running them on 1,200 Mhz with ~1.8 volts.
Should I set "Auto" on DRAM Skew on Channel A or B instead of 100 ps because Everest tells me 10T Clock Fine Delay on all 4 (?) Dimms even when I have just 2 sticks?
The lower the number of the Clock fine delay timings the better runs my system, doesn´t is?

Leave DRAM CLK Skew on Auto. They should run fine like that.

You can try lower voltage for your Memory. Run Memtest86+ V2.11 and try to find the lowest voltage. It's easier to start from 1.8V and make your way up.
Once you've found the lowest stable voltage add 2 steps higher in the BIOS and you should be fine. This works good for Windows XP X64.

[Alien Grey]

NB @ 1.55v and VTT @ 1.36v for 4Ghz - runs stable, tried 410 and it's started dying again and upping volts isn't going great.... *sigh* I think its maybe time to trade her in - really annoyed though because with the 3870X2 she ran 4.4Ghz!

~Bex

You have to know that when you use multiplier 10 the rules for overclocking change. You have to find a good balance between CPU speed and FSB.
Start with multiplier 9 and FSB 450MHz. This should possible to get stable.

You've got good memory with 450FSB and the Memory at 1200MHz you can use PL 6. QX9650@4.05GHz and PL6 isn't bad at all. If your lucky you can try to raise the FSB a little more and also overclock your memory.

[RCG_Bex]

I understand that but getting her to post a 450 is proving hard... Now, I've done 440*8 but getting it into windows with anything other than Auto on everything except cpu @ 1.35v and PLL @ 1.5 causes lock up on Windows loading screen or right before I Windows finishes kicking up

~Bex

[Alien Grey]

I understand that but getting her to post a 450 is proving hard... Now, I've done 440*8 but getting it into windows with anything other than Auto on everything except cpu @ 1.35v and PLL @ 1.5 causes lock up on Windows loading screen or right before I Windows finishes kicking up

~Bex

What board do you use? Is it a Rampage Formula or a different board with the Rampage Formula BIOS?

What BIOS do you use?

Stay with AI Clock Twister Moderate.

[Fritz_the_germ]

@Alien Grey,
the DRAM Clock Fine Delay is on Auto now.
Everest shows me 10-12-10-12T.
Is that a good or a bad timing?

I reduced my vDimm to 1,96 real and I got a BSOD.
But I changed the Ai Clock Twister to strong though.
Do you think I should stay on moderate and check up how low I can go?
With 2.02 volts vDimm prime95 (blend) stopped one worker thread immediately because of on error by rounding...

Edit: O.K. I changed the Ai Clock Twister again down to moderate and it seems to work well. That might have been the fault.

[Alien Grey]

@Alien Grey,
the DRAM Clock Fine Delay is on Auto now.
Everest shows me 10-12-10-12T.
Is that a good or a bad timing?

I reduced my vDimm to 1,96 real and I got a BSOD.
But I changed the Ai Clock Twister to strong though.
Do you think I should stay on moderate and check up how low I can go?
With 2.02 volts vDimm prime95 (blend) stopped one worker thread immediately because of on error by rounding...

Edit: O.K. I changed the Ai Clock Twister again down to moderate and it seem to work well. That might have been the fault.

Ai Clock Twister Moderate seems to be the best you can do with FSB 450 or higher and 2 X 2 Giga Memory 1081MHz or higher.

With Ai Clock Twister Strong or Stronger the timings seems to be to tight resulting in stability problems.

[RCG_Bex]

Maximus flashed to Rampage 0308.

Only thing that's changed is my RAM and GPU's - now I can't hit much past 4Ghz

http://service.futuremark.com/result...&resultType=14

~Bex

[mikeyakame]

Maximus flashed to Rampage 0308.

Only thing that's changed is my RAM and GPU's - now I can't hit much past 4Ghz

http://service.futuremark.com/result...&resultType=14

~Bex

Maximus was never really a great clocker to start with. I believe the clockgen on the Maximus is different from the Rampage. Rampage uses a more expensive higher resolution model.

[mikeyakame]

So i've got my Rampage Formula up and running in another system with a Q6600 G0 and G.Skill PI 8800 2x2gb. Flashed to 0803 bios, now its time to play!

Right now running memtest at DDR2-1000 1N command rate, 1.9v 5-5-5-15. So far so good.

Pulled off the crappy Mosfet side heatsink, and replaced it with a spare one I have from a P5Q deluxe which has a backplate mount for the 16phase, but since no rear board mosfets on Rampage it just makes for a much better mount, push pins are rubbish and user unfriendly to release.

Edit:

Update: Turns out this Q6600 doesn't play nearly as nice as my previous one at high fsb. Posted at 510mhz FSB and booted to windows only to realize It dropped 2 cores and was running 2! CPU Skew @ 300ps, NB Skew @ 200ps, DRAM Clk A @ 150ps Adv, DRAM Clk B @ 150ps Adv.

It won't even run clean at 466mhz FSB shame too!

Update2: Got a Q9550 E0 for my DFI board yesterday since my Q6600 finally got too annoying to compensate for the PLL damage. I'll start clocking this once I finish the other

[Alien Grey]

Maximus flashed to Rampage 0308.

Only thing that's changed is my RAM and GPU's - now I can't hit much past 4Ghz

http://service.futuremark.com/result...&resultType=14

~Bex

OK, that explains why it's difficult to get it stable at 450MHz.

Try the ASUS Rampage Formula BIOS 0803 and use the CPU and NB Clock Skew that are available in that BIOS version.

To give you an idea CPU Clock Skew delay 100ps and NB Clock Skew delay 100ps works very good. The NB Clock Skew delay 100ps is what I personally find working good for my system.

I don't know if the delay values will be the same on the Maximus. It's something you should try out.

Personally I don't like BIOS 0308 that much. It needs to much voltage on the NB on my system to clock it at FSB 450MHz or higher.

Don't forget to load setup defaults before you flash your board with ASUS EZ Flash II. After flashing your board do a Clear CMOS.

[mikeyakame]

New findings in MCHBAR registers I'm pretty damn amped with finding these!


CH1 Clock Drive Strength = Offset 33Dh, Dimm1 Clock Drive = 33Dh[3:0], Dimm2 Clock Drive = 33Dh[7:4]

Clock Drive = 3,
FED14330 00000000 00CC0000 02000000 00003300

Clock Drive = 5,
FED14330 00000000 01540000 02000000 00005500

CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]

DQ Drive = 8,
FED14410 02200000 02000000 00008800 40008000

DQ Drive = 6,
FED14410 01980000 02000000 00006600 40008000

CH2 Ck (clock) Drive Strength = Offset 73Dh, Dimm 3 Ck Drive = 73Dh[0:3], Dimm 4 Ck Drive = 73Dh[7:4]

CK Drive = 3,
FED14730 00000000 00CC0000 02000000 00003300

CK Drive = 5,
FED14730 00000000 01540000 02000000 00005500

CH2 DQ (data) Drive Strength = Offset 7EDh, Dimm 3 Dq Drive = 7EDh[0:3], Dimm 4 Dq Drive = 7EDh[7:4]

DQ Drive = 8,
FED147E0 00000000 02200000 02000000 00008800

DQ Drive = 6,
FED147E0 00000000 01980000 02000000 00006600

[mikeyakame]

Thank you for your reply, mikeyakame.
It´s amazing that I´m correspondending with somebody from the other side oth the world. My best greatings to australia!
But back to the dimms.
Please respect that I have to translate and to understand what you told me about the Dram Clock Delay Skew. Before it hits right into my mind could you suggest the probably best pick of the DRAM Clock fine delay for my system regarding my bios settings one post ago?

Would it be possible to set the Ai Clock Twister to strong or even stronger instead of moderate?

Possible yes, impossible to get stable at high fsb with Asus complete lack of adjustability.

I'm using DFI equivalent of strong (aggressive) with my 2GB sticks and it is worth it on this board. I have on the other hand completely adjustable Clock/Data drive strengths and individual clock/control/command skews for each channel/dimm slot. Without these it's nearly impossible to get stable at low PL without random errors. I would get random errors with strong on the Rampage with 2gb sticks.

Look at my above post, and see what values you have at those registers with BarEdit.

I'm using CLK Drive = 3, DQ Drive = 8 at the moment and aggressive (strong) is completely error free. I just checked my saved Rampage register dumps, and at 480FSB PL7 1150 DDR, the bios had CLK Drive = 6, DQ Drive = 8 set. It'll be impossible if this is the case. CLK Drive needs to be down to 3 or 4 as Powerchip ICs work well with weak clock drive and 4-500ps clock skews, and strong data drive and 700-900ps control skews.

[Alien Grey]

New findings in MCHBAR registers I'm pretty damn amped with finding these!


CH1 Clock Drive Strength = Offset 33Dh, Dimm1 Clock Drive = 33Dh[3:0], Dimm2 Clock Drive = 33Dh[7:4]

Clock Drive = 3,
FED14330 00000000 00CC0000 02000000 00003300

Clock Drive = 5,
FED14330 00000000 01540000 02000000 00005500

CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]

DQ Drive = 8,
FED14410 02200000 02000000 00008800 40008000

DQ Drive = 6,
FED14410 01980000 02000000 00006600 40008000

CH2 Ck (clock) Drive Strength = Offset 73Dh, Dimm 3 Ck Drive = 73Dh[0:3], Dimm 4 Ck Drive = 73Dh[7:4]

CK Drive = 3,
FED14730 00000000 00CC0000 02000000 00003300

CK Drive = 5,
FED14730 00000000 01540000 02000000 00005500

CH2 DQ (data) Drive Strength = Offset 7EDh, Dimm 3 Dq Drive = 7EDh[0:3], Dimm 4 Dq Drive = 7EDh[7:4]

DQ Drive = 8,
FED147E0 00000000 02200000 02000000 00008800

DQ Drive = 6,
FED147E0 00000000 01980000 02000000 00006600

Nice findings. To bad that you can't save the settings in Bar_Edit and load them at system boot like MemSet V4.0.
This should be working but it isn't or I can't seem to find how to do it with Bar_Edit.

[mikeyakame]

Ask Felix in Memset thread!

[Fritz_the_germ]

Thank you for your reply!
The setting strong or even stronger will make my system unstable. So I set it back to moderate.
The vDimm is 1,98v real and I think it could be lower.

I installed BarEdit vers. 3 and saved the bar text with a sreenshot below:

What am I supposed to do now?

@mikeyakame,
you have posted yesterday:
1T = whatever the base step degree value is necessary to give the calculated delay skew value at any one point in time. If MCH calculates 300ps dimm1, 360ps dimm2, 395ps dimm3, 455ps dimm4, then base step degree will be whatever the closest step selection is available which can be used for channel a clock fine delays for example. Step might be 90ps in this example as all 4 dimm flight delays will be pretty close to the calculation for x amount of degrees using that base step selection. 90ps @ 4 degrees gives 360ps, 90ps @ 5 degrees gives 450ps, 1T = 1 degree of base step
The slot 2 and 4 are occupied with one stick.
To get the timings about being even I should set 100ps advanced to the slot 2 that means dimm2 would have ~460ps and about as much as the dimm4 with 455ps.
Did I get you right or wrong?

[mikeyakame]

Thank you for your reply!
The setting strong or even stronger will make my system unstable. So I set it back to moderate.
The vDimm is 1,98v real and I think it could be lower.

I installed BarEdit vers. 3 and saved the bar text with a sreenshot below:

What am I supposed to do now?

@mikeyakame,
you have posted yesterday:
1T = whatever the base step degree value is necessary to give the calculated delay skew value at any one point in time. If MCH calculates 300ps dimm1, 360ps dimm2, 395ps dimm3, 455ps dimm4, then base step degree will be whatever the closest step selection is available which can be used for channel a clock fine delays for example. Step might be 90ps in this example as all 4 dimm flight delays will be pretty close to the calculation for x amount of degrees using that base step selection. 90ps @ 4 degrees gives 360ps, 90ps @ 5 degrees gives 450ps, 1T = 1 degree of base step
The slot 2 and 4 are occupied with one stick.
To get the timings about being even I should set 100ps advanced to the slot 2 that means dimm2 would have ~460ps and about as much as the dimm4 with 455ps.
Did I get you right or wrong?

Well what I mean is thats just a rough guess. I haven't worked out how to calculate the correct autodetect ps values yet, still working on that. I know where they are held roughly, but its a mystery to me how they are formatted. Tried a few different approaches and one of them showed progress but I can't replicate it on all samples.

On moderate though, Clock skew is usually around 350-500ps on each channel, and channel b should be have slightly higher value.

It's a misleading adjustment. The actual skew is a delay from host fsb to memory slot, so channel b will naturally have more delay than channel a because channel b is farther from MCH.

Should be safe to assume you can safely delay channel b upto 50ps more than channel a if It helps. Same with other way around. There shouldnt be more than 50-60ps between both channels, even worst case. Best case its about 25-35ps which is most of the time.

You also have advance back to front!
Delay adds to the base skew, Advance subtracts from it.

When you advance the clock, it'll be driven earlier from the memory controller so it arrives earlier than anticipated.

If you delay the clock, the clock will be held for longer than necessary before it is driven to the memory slot.

Delay 50ps on 450ps, is 500ps delay for flight, hold clock 50ps more before drive.
Advance 50ps on 450ps, is 400ps delay for flight, hold clock 50ps less before drive.

Generally -+100ps is most on either channel from where the base is you can advance or delay the clock drive. Any more and it arrives too early and kills performance, or too late and MCH reads back wrong data and kills performance or corrupts reads.

Rule of thumb is, AI Clock Twister strength (cross clocking during mch/dram access) as you tighten up dram cross clocking delay loop skews with this, you either advance dram clock skews 100-150ps on both channels if you have enough headroom, or you loosen up MCH read delay phase skewing by raising Performance level +1 and using phase pull-ins to drop channel 1 to next tighter PL and channel 2 at current PL. If that doesnt work you go next PL down.

Gains from tight Read Delay on MCH side are much greater than gains from holding out (delaying) DRAM clock, command and control drives.

If you can balance tight PL with aggressive DRAM cross clocking skews then that's great. I havent used any 2gb sticks that would do it with consistency. I could run 4x1gb with Stronger & PL 6 at 475mhz fsb, but 2gb sticks wont even get through bios without locking up.

[Fritz_the_germ]

O.K. Mike, there are many things a have learned about the "skewing clocks". Do know a good book about the Intel systems to improve my knowledge?
The vendors sale their boards with a thin paged "user guide" which contains a little about the bios options. But the regular user doesn´t know what the hell is doing setting clock skews, pull-in phase and so on.

But the most interesting point is that the Asus boards are pretty buggy epsecially the Asus bios programmers seem to go their own buggy way compared to the DFI boards. Do you have a recommandation for a good DFI board?

And at last: Would you say a fsb divider 1:1 brings out more performance than 4:3? AnandTech considers 4:3 brings out more read performance:
http://www.anandtech.com/mb/showdoc....208&p=1:shrug:

[Alien Grey]

Ask Felix in Memset thread!

I did that. SoLoR knows how to do it and posted in the MemSet thread how it should be done.

[Alien Grey]

Loading settings at startup with Bar_Edit V3.0 and Windows XP X64 doesn't seem to work.

I tried what SoLoR said but it's not working.

[SoLoR]

Loading settings at startup with Bar_Edit V3.0 and Windows XP X64 doesn't seem to work.

I tried what SoLoR said but it's not working.

well try to do this manualy: http://rapidshare.com/files/209947592/BAR_Save.zip here is my C:\BAR_Save (its default location BAR_Edit creates to load at startup). Then make shortcut to startup folder to BAR_Edit.exe from BAR_Save. In there you will find BAR_Edit.ini and just change addresses & values you want to change.