Quote Originally Posted by Grnfinger View Post
500 FSB is a tough nut to crack with this new chip....

45nm quad users running FSB of 465 or higher, whats your vNB set at?
My final settings, rock stable at 8*475. I don't have time now, to play more. But this FSB, as you can see, is really easy to achieve !

My settings:
Code:
Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 8
FSB Frequency: 475
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: 333
DRAM Frequency: DDR2-1140MHz

DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto

DRAM Timing Control: Manual

1st Information:

CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay: Auto
Row Refresh Recycle Time: Auto
Write Recovery Time: Auto
Read to Precharge Time: Auto

2nd Information:

Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto


3rd Information:

Write to PRE Delay: Auto
Read to PRE Delay: Auto
PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Disabled
Ai Clock Twister: Stronger
Ai Transaction Booster: Manual

Common Performance Level: 8
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled

PCIE Frequency: 100

CPU Voltage: 1.275
CPU PLL Voltage: 1.55
FSB Termination Voltage: 1.325
DRAM Voltage: 1.9375
North Bridge Voltage: 1.45
South Bridge 1.5 Voltage: 1.55
South Bridge 1.1 Voltage: 1.15

CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto

CPU Configuration

Ratio CMOS Setting: 8
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Enabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled

Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
I will try with e.v.o's BIOS this weekend to see, what will happen