X48 Rampage Formula Preview.

[mikeyakame]

I havent found I needed to use any NB Skew except when I was playing around 1N command rate at DDR2-1066, 100ps NB, 200ps CPU made the most difference.

Otherwise CPU 100ps NB Normal should be pretty safe.

CPU being farther from the MCH/NB means it is more prone to clock drive deviation. FSB is driven right off BCLK so unless clock jitter directly created as a result of NB Voltage there shouldn't be much need to skew the NB clock unless it's for the purpose of aligning all the clocks with the IOH if its deskewed too much

There are 4 important Clock domains to consider.

CPU Clock, MCH clock, DRAM clock, IOH clock.

IOH (SB) has a few land pins which reference/sample directly from the CPU, so corrections to IOH Clock Drive skew are possibly made based on CPU Clock Drive skewing. I don't know for sure, but being so far away on the board it would make sense to reference the farthest Clock Domain to help out with strobe timing.

Host FSB BCLK is driven from the Analog PLL Clock Generator. This is located right below the Northbridge chip.

CPU Clock Drive is referenced from Host FSB BCLK.
MCH(NB) Clock Drive is referenced from Host FSB BCLK.
IOH Clock Drive is referenced from both Host FSB BCLK and CPU Clock.

DRAM Clock Drive is referenced from MCH Clock from what I can tell, since MCH is DRAM Controller and MCH is responsible for Read Delay timing during Cross Clocking Procedure.

Read Delay is the necessary turnaround between MCH request DRAM READ on one differential clock falling edge (ie low clock#), then a CPU requested FSB READ on the following differential clock falling edge (ie high clock). This is a procedure that has no direct handshaking between either end, rather relies on MCH reading data from DRAM, burst reading it onto the FSB host bus, then the CPU doing a blind read exactly half a clock period later whether data is there or not.



FSB BCLK sampling is done closest to NB, so NB Clock Skew will be the most resistant to deviation, and so far it seems from the responses of a few guys who are using same as me, CPU 100ps/NB 0s that this is very true. If I delay NB 100ps without delaying CPU 100ps more, and advancing DRAM CLK skew by 100-150ps, then I will get near instant BSOD's and pretty unstable operation even to then.

If your board needs it then thats ok, but unless you are using over 500mhz FSB and even more theres a good chance you probably should be safe with Normal NB Clock Skew.

100ps is a lot so unless the clock jitter is causing a deviation of more than half that amount (50ps), then don't worry. 100ps at 500mhz fsb is 1/20 clock period. It's quite a big amount and if its too much you'll end up more than likely corrupting CMOS or system files.

First thing I did was try different NB Clock Skew values on my board, and any more than 100ps and every time it resulted in no more CMOS data Had to redo all settings each POST, because they would completely vanish. NB Clock Skew is dangerous so believe me when I say if you don't need to change it then don't. It's only if you are pushing some heavy Vnb that it will show some serious benefits vs the risk of too much delay skew.

8GB Ram , 1.51-1.55v+ Vnb or Command Rate 1N + High DDR freq are the only cases I can think of which may need extra NB Clock Skew.

Edit:

Let me add one final concept to this post.

If you are highly experienced with fine tuning the bios settings and have a good understanding of the AGTL+ FSB design concept and how the CPU<->MCH<->DRAM procedure works at a low level, and you don't mind nuking a few OS installs in the process, then the following might interest you

With the precise balance of CPU Clock Skew, NB Clock Skew, PL phase pull-ins, GTL Refs, DRAM CTL Ref, DRAM secondary/tertiary timings and Vnb you can further tighten Performance Level beyond the point that is unpostable
Thats the key to tightening PL beyond the physical divider limit you reach in most conditions. Ie if PL=7 is limit for 12:10 divider at 500FSB, then PL=6 and even tighter is possible if you can balance the whole system on a pin, ie the timing of all strobes from end to end is near PERFECTION!

it's possible without a multi channel oscilloscope / logic analyzer, though you'd need a lot of patience,a good spare week or two to get it right, and a good OS ghost image to restore everytime you nuke it from being slightly wrong.