Amd steppings and what they mean.........

[chew*]

Instead of cluttering up another thread i decided to make one so here goes.....

OK first we need a picture of a cpu........Particle I used yours again I hope you don't mind

Photo courtesy of particle as long as he lets me use it.


So here we have a typical 940 CPU

Lets start with the 5 digit code CACVC

First letter is the production/release code if this was an ES chip it would be an A. They are using the letter C for current production release chips although they don't always use C

2nd letter is the Core Cache code It will probably be different with lets say X3chips and X2's with less cache

3rd and 4th letter identify the memory controller revision. This apparently is a CV revision memory controller.

5th letter is usually a revision code
C = Deneb most likely in this case......

Next we move onto the 4 digit number code......
year and week

The chip pictured appears to be made in 08 week 50 so around december 14th...

Now the last 4 has always been vague but i've always believed them to be the code that determined who tested, time of day, etc etc.....I really don't think its as pertinent unless the guy testing was half in the bag (not likely)

Now to the bottom of the chip.

Last 6

L I think ( it's been a while ) means Lot as in Lot # ****CORRECTION**** the letter before th batch is a date code......

the last 5 tell you what batch it came from and what # it was in the batch ****Correction**** the 8 in this case means 2008

This is batch 80000 which will probably go up to 81000 and this particular chip was # 74 out of 1000.

Anyway this concludes my lesson on stepping and batch numbers for now....more to follow in the future......

****EDIT**** the purpose of the lower line for AMD is it's a serial # for them to specifically ID a chip...whether for RMA purposes or to keep track of chips not specified for retail or other reasons unbeknown at this time.

[Particle]

Very nice post as usual!

[Sparky]

Has that 5 digit code always been that way? I remember my Opteron 165 was a CCBBE which was known to do well on air/water (and it did!) but hated cold, while CCBWE was bad for air/water but loved volts and was better under phase. And it has been suspected that the mem controller was the main reason for the coldbug, so mem controller BB was bad with cold while BW was better with cold but bad with air/water?

/random musing

Chew, I am glad to see you in here. Good stuff man. Thanks for sticking it out through some of the guys who seemed to want to make your life miserable here. Keep it up

[chew*]

Been that way since they went with IMC's, wasn't prior to 754.

If you remember BH was the best for getting around the coldbug so BW wasn't to far a distant cousin, BB sounds like a much earlier version which could explain its dislike for cold.

Voltage requirements could have been due to something else with your chips......remember the letter on the PCB Appears amd is still making T stamps in the PCB still, I would need pics of other users chips but i'm betting they still stamp N on some of the pcb's as well.

[Oldguy932]

I'm voting sticky.

[mongoled]

This was posted in another thread but no one commented on it.

OC Detective is talking abt the numbers AFTER the date

First Digit is either R through to X for Monday to Sunday or A through to G for same. M means mixed assembly lot.
P merely means Penang
3rd digit is the sequential batch of cores used in assembly - so if they are using the first batch for that day its an A second batch is B and so forth. M means the cores used in the assembly came from different batches.
The existence of a W for the 4th letter means mixing of wafer lots in the core fabrication was prohibited. Its absence means the wafer lots could be mixed when making a batch of cores.
0450 etc is self explanatory and is the week of assembly.

From

http://www.xtremesystems.org/forums/...&postcount=133

Will try to find where OC Detective originally posted this, as if I remember correctly that is where most of the discussion regarding steppings took place.

-- EDIT --

Found the information I was looking for @ ocforums, hitechjb1 had done some fantastic work over there regarding AMD and A64 settings/database. Full credits to him for the link below

CODES AND CARRIER OPTIONS.PDF

I havnt found out how dated this document is, there maybe newer one.....

[largon]

Curiously, Thunderbird model C K7s, which introduced FSB266 and copper interconnects were the first AMD CPUs to carry the 5-letter code, earlier aluminum-based Thunderbirds were only marked with a 4-letter stepping code. Since copper interconnects are much trickier than alu-ics to manufacture and the configuration of the copper layer is crucial to the chip's electrical properties it might be a reason to add a 5th letter into the originally 4-letter stepping code.

My guess is, the 3rd and 4th letters mark ASIC revisions, one for the revision of the silicon and the other for the metal interconnect.

Similar to, for example, the spin/silicon/metal-ic codes laser-etched on AMD/ATi GPUs ("A13" for retail R600, eg.)

[biohead]

FCG (freecableguy) had explained this years ago... let me dig it up.

http://www.xtremesystems.org/forums/...ad.php?t=87182

s7e9h3n and I have been working on decoding the AMD memory controller/stepping information found on all new AMD processors for awhile now. This information is the combination of 5 letters and numbers found on the second line, immediately proceeding the year/week production code.

Example: CABNE

1st letter: "production/release code"
Pre-production or early samples have an "A" here where final production batches will be a "C" (for current chips). Some may recall that Venice samples where seen in the wild as "ABBLE" and current production runs are "LBBLE". While complete understanding of this is unknown at this time, it is clear that this has something to do with early samples.

2nd letter: "core cache code"
A = single core, 1MB
B = single core, 512KB
C = dual core, 1MB (each)
D = dual core, 512MB (each)

Note: 'Toledo' cores (1MB) with half the cache disabled will still be coded as "C". Therefore, you can see earlie 4600+ samples as ACXXX with only 512KB per core enabled.

3rd and 4th letters/numbers: "memory controller revision"
Works like a counter using all letter of the alphabet and digits 1-9. 3rd letter increments when running though all available 'steppings' as noted by the 4th letter.

FX-55: XXA2X
FX-57: XXBNX
FX-57 (new stepping)/FX-60: XXB2X
3700+ (new stepping): XXB3X
...
and so on...

5th letter: "revision code"
C = rev C (as in CG Clawhammers)
D = rev D (as in D0 for CBBID chips....)
E = rev E (as in the rev E 'San Diego' core)

-FCG & s7e9h3n

the 4-letter code after year+week is the packaging code. i think it means what day of the week.

[PepsiLove]

Thanks =), I always wondered how the letters/numbers corresponded with date/batch.

[largon]

"Memory controller revision -explanation" doesn't make sense considering K7s had a 5-letter code too. And the whole IMC-theory is just speculation as stated by s7e9h3n. Then there's this question; why would they keep on continuously revising the IMC alone since there's no problem with it in the first place?


Infact, the appearance of the 5th letter matches exactly with introduction of copper interconnects back with Thunderbird C model K7s... And tweaking the metal/silicon layers is everything for what comes to yields and frequency scaling.

[soundood]

nice chew*

allways nice to refresh peeps on this coding, i only wish that someone from ocinside.de would update thier interactive product ID guide from Athlon 64 to present day.

here is the guide, i still harp back to it the odd time, might be handy for those still running an Athlon 64.

http://www.ocinside.de/html/workshop...roduct_id.html



ahhh the oldish days...lol, pin mods and 133 mhzs

[knopflerbruce]

Instead of cluttering up another thread i decided to make one so here goes.....

OK first we need a picture of a cpu........Particle I used yours again I hope you don't mind

Photo courtesy of particle as long as he lets me use it.


So here we have a typical 940 CPU

Lets start with the 5 digit code CACVC

First letter is the production/release code if this was an ES chip it would be an A. They are using the letter C for current production release chips although they don't always use C

I wouldn't call these chips engineering samples, they're not. An ES has normally eng sample or something written on the chip. my guess is that these chips were some kind of retail test batches, like if they do what they should they release them - if not, they tweak a bit more. Alot of Axxxx batches were sold through retail channels, however at least a few of them were kept for some reason (for instance, I got an AAAXC 0421(something) from a woman, who got it from her bf/husband, who got it from a guy that works for AMD. The only "published" result with that stepping is mine). AMD used a whole BUNCH of different letters except A and C, but I can't really tell why. perhaps they did some kind of small tweaks between different "revisions", I dunno.

2nd letter is the Core Cache code It will probably be different with lets say X3chips and X2's with less cache

If there will be less cache PHYSICALLY on the die, the X3's and X2's will have a different letter than A (perhaps B and/or C, but on K8 they used D, E and F as well). If they just disable cache it will be A for all chips.

3rd and 4th letter identify the memory controller revision. This apparently is a CV revision memory controller.

I'm not sure it identifies the memory controller revision, but I can't come up with a better idea I just wonder who said that that pair of letters identifies the memory controller for the first time, it would be nice to see the reason behind that conclusion. Just note that there are chips from the 754 era (130nm) that, if this is correct, have AA memory controllers. Also note that thereare 9850BE's with that "memory controller" as well. There are also alot of similar memory controllers bewteen 939 and AM2 (like BA, BB, B9, BU(?), BF, BG)

{quote]5th letter is usually a revision code
C = Deneb most likely in this case......[/quote]

It's the core revision, like K10, rev.3 (A.B.C). Agena was rev. 2 (B), never saw any A chips, though. This is the same as on K8, OLD Clawhammers has steppings like AAABB, then newer ones (+ newcastles) had CAAXC etc, then we had winchesters - CBBHD, Venice etc, CAB1E +++, Windsor CCB8F etc and finally brisbanes with the NAA9G's etc

Next we move onto the 4 digit number code......
year and week

The chip pictured appears to be made in 08 week 50 so around december 14th...

Now the last 4 has always been vague but i've always believed them to be the code that determined who tested, time of day, etc etc.....I really don't think its as pertinent unless the guy testing was half in the bag (not likely)

The first letter (A-G, R-X) is production day, I guess - maybe before or after lunch? I don't know. The second letter is location, P means Malayisia, and A means China (probably the lcation of the plants, I don't know). I'm pretty sure I've seen F's here as well on some newer Brisbanes. The third letter is some kind of wafer ID-thing, I think. M indicates some kind of "mix", perhaps the others are "ordered" after some kind of rule AMD made. I can't tell what, though.

Now to the bottom of the chip.

Last 6

L I think ( it's been a while ) means Lot as in Lot #

L is the 12th letter in the alphabet. It has something todo with December. This is not a coincidence, it makes sense on nearly ALL AMD chips I've seen so far - with a few exceptions. Perhaps the "L" identifies the month the chip was "put together", and the week/day code in the line above identifies the day the core itself was made? (they're not two labels for the same thing, sometimes they don't match - I have a few samples in my collection that shows that).

the last 5 tell you what batch it came from and what # it was in the batch

This is batch 80000 which will probably go up to 81000 and this particular chip was # 74 out of 1000.

The "8" refers to 2008. and the last 4 is some kind of wafer-ID (like they have 1200 dies on a wafer, they label them 0000-1199).

The numbers BEFORE the L probably tells you which wafer it came from, but I have no clue about those details. I can see some patterns, but I can't get any useful info out of it. Still trying, though

[biohead]

lots of info itt

[knopflerbruce]

lots of info itt

This is what i do, remember?

[chew*]

Trust me its a memory controller revision, and not necessarily a revision but a way of measuring it........no matter how hard you try it would be almost impossible to make a wafer identical every single time...just like twins even though genetically Identical are different They just use that code to identify it. It's quite obviously a progressive identity, as they are on to CV now....I worked with S7 on this i'm quite aware of the old thread and we did extensive research before posting findings.

It could also mean something else but we do know for a fact that whatever it is , it effects the memory controller specifically so this is how we ID it.

What i find intersting is the added 2 letters in between the 5 digit stepping and date code.... AC.

[largon]

That would mean the proverbial "IMC stepping" has no effect at all on core OC'ability of K10/K10.5s. If future observations contradict this hypothesis then a new theory is required.

[Halk]

Thanks again for explaining this Chew!

[chew*]

That would mean the proverbial "IMC stepping" has no effect at all on core OC'ability of K10/K10.5s. If future observations contradict this hypothesis then a new theory is required.

Well there's a simple way to prove disprove this.........phenom 1 coldbugs like a mother.........show me a phenom 1 with the CV revision.....

I plan to do another database with AM3.....really all the info we know from S939 is moot now and may not be able to be carried over. We shall see what Am3 steppings tell us in the near future.

I find date code's have more to do with ocability than anything, for instance 0543 = 2005 week 43 chips were ok overclockers but nothing to write home about ( 3 gig phase ). 9/10 times if we see a few chips from a date code with high yields the trend is most chips from that period scale well.

The cold bug btw had alot to do with memory, those that coldbugged could scale decent but not 1/1 with memory. Although it appears PH2 doesn't coldbug I would be curious to see how it clocks memory while cold, I'd muster a guess that some chips are going to be able to clock memory higher than others while cold..where as when not cold they clock memory fine.

Right now limited to ddr 2 we may not be able to acchieve that point, DDR 3 is another story.......

[Oldguy932]

So I got curious and looked at the batch of my Opty 1356, one of the quad core single socket barcelonas. Its an 80022, which is really good so it makes sense why I could get to 240htt without a problem but past that the mobo would just crap out because the cpu wasn't supported entirely.

[chew*]

BTW bruce thx for clearing some of those up, My memory was vague at best on the batch line save the last 4 numbers.

I knew the 4 after the date had something to do with that but I never found those to be crucial to anything.

Any idea on the monkey wrench thrown into the mix? AC between the stepping and date code? Could that mean a chip supporting ACC?

[possessed]

What i find intersting is the added 2 letters in between the 5 digit stepping and date code.... AC.

also noticed those 2, maybe integrated acc?

[largon]

Agena too has those two additional letters so... Not ACC related.

[knopflerbruce]

Agena too has those two additional letters so... Not ACC related.

Perhaps Lvl 3 cache-related?

[largon]

Could be.
It's certainly something K10 has and K8 doesn't.

[chew*]

I would tend to agree with you on that bruce, or at least it makes sense.