Intel Xeon 5570: Smashing SAP records.

[savantu]

I love how "Intel used L3 first on the P4" yet don't recall the K6-III that had L3 and that was where the TLB error came from and was never fixed.

BS.

There is no relation between TLB bugs on similar designs ( K10/Nehalem) , not to mention CPUs designed 10 years.

Each patient with its own disease.