New Memory Tweaker for Intel Chipsets

[mikeyakame]

Felix

Just curious in which manner you are using to write the pci registers?
I think I read that you are using a ring0 driver, so if thats the case you are attempting to write the NHM pci registers while at priv level 0.

Ie. transitition from priv 3 to 0 and then back to 3 by SYSENTER/SYSEXIT instructions right? The pci registers are definitely RW flagged not RWO. If you are using WRMSR to mov the ESP, EIP, CS data to their corresponding msr offset address, then making a SYSCALL or SYSENTER, and then executing the instructions pointed to by IA32_SYSENTER_EIP msr you wrote before making the call.

If that is along the lines of the method you are using and its not working, I'm wondering if it is possible to switch to real-address mode without causing a GP exception and manually set the registers bits if its possible to use the pci offset:address in real-address mode that is. If the PCIBAR isn't locked which it shouldn't be since it's used for counters and such too, and the bios can change its values I'm thinking it may not be that it can't be done, but rather the precursors for doing it. I've read briefly through the I7 datasheets and from what I understand that there are rules setup for access control to certain address ranges and registers. If you hadn't come across this it, my understanding is on different bus interconnects there are different access rights for say pcie, qpi, dmi, smbus, etc based calls depending on what the devices on that end need priviledge to do. If the origin of the call is say QPI bus, then there are rules setup to restrict access when reading and or writing certain hw address registers or memory offset locations.

I may be understanding that wrong, but if i'm not then a theory I have is if this was true, what if a roundabout method was used to write rule restricted registers by forwarding the call as such through a bus that matches the access control to write that register, since it checks source flag to match access it might be another means which the bios does it, since Intel would have let all the bios engineers know exactly how to write the registers if protected in such a way that opening them up for write access could mean that if you write one RW reg it may be possible to change any that arent RWO or RO. This just came to mind, and thought it was worth sharing. If I come up with anything more that's worth mentioning I'll pass it over.

Intel engineers would have put in place more than 1 method of writing pci registers since we know the bios can do it and the rules for the bios doing it should be no different than your app doing it, just a matter of exposing the means if its not documented.

[vld]

why is there no performance level changer for pm45 ?



why is there no performance level changer for pm45 ?

[GrossmeisterB]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

[BenchZowner]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

It's been said a few times already.
Chipset limitation.

[Ace-a-Rue]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

if you mean memory tweaker can not change it, you are not alone...in order to make a change to CAS, the puter normally has to shutdown to effect the change or at least have a restart after making the change from the bios.